公开(公告)号：EP0197708A3

公开(公告)日：1988-01-13

申请号：EP86302239

申请日：1986-03-26

申请人： STC PLC

发明人： Wong, Andrew Chi-Chung ,  Rolley, Robert

IPC分类号： H03D03/00

CPC分类号： H03D3/007 ,  H03B27/00 ,  H03D3/006 ,  H03D2200/005 ,  H03D2200/0054

摘要： A digital zero IF circuit having first and second signal paths 111, 110 to which a radio frequency signal is applied, each path including a sampling and digitising means 121, 12Q and a digital filter means 13l, 13Q, the circuit including a clock generator arranged to generate two clock pulse trains in quadrature phase relationship, each sampling means being operated in response to a respective one of the clock pulse trains.

摘要翻译： 具有施加射频信号的第一和第二信号路径111,110的数字零中频电路，每个路径包括采样和数字化装置121,12Q和数字滤波器装置13I，13Q，该电路包括布置的时钟发生器 以产生正交相位关系的两个时钟脉冲串，每个采样装置响应于相应的一个时钟脉冲串而工作。

公开(公告)号：EP0155776A1

公开(公告)日：1985-09-25

申请号：EP85301261.5

申请日：1985-02-25

申请人： STC PLC

发明人： Wong, Andrew Chi-Chung ,  Fearnhead, Graham Roy ,  Gale, Simon John

IPC分类号： G01S5/14 ,  G01S11/00

CPC分类号： G01S19/29

摘要： A NAVSTAR receiver in which the received signals are processed to produce digitised quadrature signals (l,Q) at zero i.f. Baseband phasor rotation to effect Doppler tracking in the receiver loop is accomplished by deriving digital signals representing sin wT and cos wT for the required rotation angle wT, multiplying the quadrature signals separately and summing the outputs according to the algorithm I' = I cos ωT + Q sin ωT and Q 1 = Q cos ωT - | sin ωT, where |& Q are the digitised quadrature signals.

公开(公告)号：EP0197708A2

公开(公告)日：1986-10-15

申请号：EP86302239.8

申请日：1986-03-26

申请人： STC PLC

发明人： Wong, Andrew Chi-Chung ,  Rolley, Robert

IPC分类号： H03D3/00

CPC分类号： H03D3/007 ,  H03B27/00 ,  H03D3/006 ,  H03D2200/005 ,  H03D2200/0054

摘要： A digital zero IF circuit having first and second signal paths 111, 110 to which a radio frequency signal is applied, each path including a sampling and digitising means 121, 12Q and a digital filter means 13l, 13Q, the circuit including a clock generator arranged to generate two clock pulse trains in quadrature phase relationship, each sampling means being operated in response to a respective one of the clock pulse trains.

摘要翻译： 具有施加射频信号的第一和第二信号路径11I，11Q的数字零中频电路，每个路径包括采样和数字化装置12I，12Q和数字滤波器装置13I，13Q，该电路包括布置成 为了产生正交相位关系的两个时钟脉冲串，每个采样装置响应于相应的一个时钟脉冲串操作。