公开(公告)号：EP1220088A2

公开(公告)日：2002-07-03

申请号：EP01310644.8

申请日：2001-12-19

申请人： STMicroelectronics, Inc.

发明人： Faraboschi, Paolo ,  Starr, Alexander J. ,  Brown, Geoffrey M. ,  Homewood, Mark Owen

IPC分类号： G06F9/312

CPC分类号： G06F9/3834 ,  G06F9/30043 ,  G06F9/3816 ,  G06F9/383 ,  G06F9/3842 ,  G06F9/3861

摘要： There is disclosed a data processor comprising: 1) an instruction execution pipeline comprising N processing stages for executing a load instruction; 2) a status register for storing a modifiable configuration value, the modifiable configuration value having a first value indicating the data processor is capable of executing a misaligned access handling routine and a second value indicating the data processor is not capable of executing a misaligned access handling routine; 3) a misalignment detection circuit for determining if the load instruction performs a misaligned access to a target address of the load instruction and, in response to a determination that the load instruction does perform a misaligned access, generating a misalignment flag; and 4) exception control circuitry capable of detecting the misalignment flag and in response thereto determining if the modifiable configuration value is equal to the first value.

摘要翻译： 有游离缺失光盘的数据处理器，包括：1），以指令执行管线，其包括N个处理阶段用于执行加载指令; 2），用于存储可修改的配置值的状态寄存器，具有第一值指示所述数据处理器中的修改的配置值是能够执行未对齐存取处理例程和第二值指示所述数据处理器的不能够执行未对齐存取处理的 常规; 3）用于确定性采矿一个偏差检测电路，如果加载指令执行未对齐存取加载指令的目标地址，并且响应于没有加载指令并执行未对齐存取的确定，产生的未对准标记; 和图4），其能够检测所述未对准标志，并响应于此确定性采矿异常控制电路，如果修改的配置值等于firstValue。

公开(公告)号：EP1220091A2

公开(公告)日：2002-07-03

申请号：EP01310630.7

申请日：2001-12-19

申请人： STMicroelectronics, Inc.

发明人： Faraboschi, Paolo ,  Jarvis, Anthony X. ,  Homewood, Mark Owen

IPC分类号： G06F9/38

CPC分类号： G06F9/3891 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/3802 ,  G06F9/3853 ,  G06F9/3885

摘要： There is disclosed bundle alignment and dispersal circuitry for use in a data processor. The data processor comprises: 1) C execution clusters, each of the C execution clusters comprising an instruction execution pipeline having N processing stages for executing instruction bundles comprising from one to S syllables, wherein each the instruction execution pipelines is L lanes wide, each of the L lanes for receiving one of the one to S syllables of the instruction bundles; 2) an instruction cache for storing a plurality of cache lines, each of the cache lines comprising C*L syllables; 3) an instruction issue unit for receiving fetched ones of the plurality of cache lines and issuing complete instruction bundles toward the C execution clusters; and 4) alignment and dispersal circuitry for receiving the complete instruction bundles from the instruction issue unit and routing each the received complete instruction bundles to a correct one of the C execution clusters as a function of at least one address bit associated with each of the complete instruction bundles.

摘要翻译： 公开了用于数据处理器的捆绑对齐和分散电路。 数据处理器包括：1）C个执行群集，每个C执行群包括一个指令执行流水线，该指令执行流水线具有N个处理级，用于执行包括从一个到S个音节的指令束，其中每个指令执行管线是L通道， 用于接收指令束中的一个到S个音节的L通道; 2）用于存储多个高速缓存行的指令高速缓存，每个高速缓存行包括C * L个音节; 3）指令发布单元，用于接收所述多个高速缓存行中的取出的数据，并向所述C个执行簇发出完整指令束; 以及4）对准和分散电路，用于从指令发布单元接收完整的指令束，并将所接收的完整指令束中的每一个作为与所述完整指令中的每一个相关联的至少一个地址位的函数， 指令包。

公开(公告)号：EP1220089A2

公开(公告)日：2002-07-03

申请号：EP01310643.0

申请日：2001-12-19

申请人： STMicroelectronics, Inc.

发明人： Homewood, Mark Owen ,  Vondran, Gary L. ,  Brown, Geoffrey M. ,  Faraboschi, Paolo

IPC分类号： G06F9/32 ,  G06F9/38

CPC分类号： G06F9/30058 ,  G06F9/3885

摘要： There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address, (ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The- data processor then uses the computed branch condition to select one of the branch address or the next program counter address.

摘要翻译： 有游离缺失盘具有集群架构确实包含至少一个支化簇，至少一种非分支群集和远程条件分支的控制电路的数据处理器。 每个簇的是能够计算分支条件，虽然只分支群集是可操作以执行分支地址的计算。 遥控条件分支的控制电路，所有这一切都与每个集群相关联的，可操作以响应于感测到在一个非分支群集的条件分支指令于（i）使所述分支群集来计算分支地址和下一个程序计数器 地址，（ⅱ）使所述非分支群集来计算分支条件，以及（iii）从所述非分支群集通信所计算的分支条件到分支群集。 所述数据处理器然后使用计算分支条件来选择分支地址或下一个程序计数器地址中的一个。

公开(公告)号：EP1220088B1

公开(公告)日：2009-06-03

申请号：EP01310644.8

申请日：2001-12-19

申请人： STMicroelectronics, Inc.

发明人： Faraboschi, Paolo ,  Starr, Alexander J. ,  Brown, Geoffrey M. ,  Homewood, Mark Owen

IPC分类号： G06F9/312

CPC分类号： G06F9/3834 ,  G06F9/30043 ,  G06F9/3816 ,  G06F9/383 ,  G06F9/3842 ,  G06F9/3861

公开(公告)号：EP1220088A3

公开(公告)日：2006-04-26

申请号：EP01310644.8

申请日：2001-12-19

申请人： STMicroelectronics, Inc.

发明人： Faraboschi, Paolo ,  Starr, Alexander J. ,  Brown, Geoffrey M. ,  Homewood, Mark Owen

IPC分类号： G06F9/312

CPC分类号： G06F9/3834 ,  G06F9/30043 ,  G06F9/3816 ,  G06F9/383 ,  G06F9/3842 ,  G06F9/3861

摘要： There is disclosed a data processor comprising: 1) an instruction execution pipeline comprising N processing stages for executing a load instruction; 2) a status register for storing a modifiable configuration value, the modifiable configuration value having a first value indicating the data processor is capable of executing a misaligned access handling routine and a second value indicating the data processor is not capable of executing a misaligned access handling routine; 3) a misalignment detection circuit for determining if the load instruction performs a misaligned access to a target address of the load instruction and, in response to a determination that the load instruction does perform a misaligned access, generating a misalignment flag; and 4) exception control circuitry capable of detecting the misalignment flag and in response thereto determining if the modifiable configuration value is equal to the first value.

公开(公告)号：EP1220091B1

公开(公告)日：2009-08-05

申请号：EP01310630.7

申请日：2001-12-19

申请人： STMicroelectronics, Inc.

发明人： Faraboschi, Paolo ,  Jarvis, Anthony X. ,  Homewood, Mark Owen

IPC分类号： G06F9/38

CPC分类号： G06F9/3891 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/3802 ,  G06F9/3853 ,  G06F9/3885

公开(公告)号：EP1220089B1

公开(公告)日：2008-12-31

申请号：EP01310643.0

申请日：2001-12-19

申请人： STMicroelectronics, Inc.

发明人： Homewood, Mark Owen ,  Vondran, Gary L. ,  Brown, Geoffrey M. ,  Faraboschi, Paolo

IPC分类号： G06F9/32 ,  G06F9/38

CPC分类号： G06F9/30058 ,  G06F9/3885

公开(公告)号：EP1220091A3

公开(公告)日：2002-12-04

申请号：EP01310630.7

申请日：2001-12-19

申请人： STMicroelectronics, Inc.

发明人： Faraboschi, Paolo ,  Jarvis, Anthony X. ,  Homewood, Mark Owen

IPC分类号： G06F9/38

CPC分类号： G06F9/3891 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/3802 ,  G06F9/3853 ,  G06F9/3885

摘要： There is disclosed bundle alignment and dispersal circuitry for use in a data processor. The data processor comprises: 1) C execution clusters, each of the C execution clusters comprising an instruction execution pipeline having N processing stages for executing instruction bundles comprising from one to S syllables, wherein each the instruction execution pipelines is L lanes wide, each of the L lanes for receiving one of the one to S syllables of the instruction bundles; 2) an instruction cache for storing a plurality of cache lines, each of the cache lines comprising C*L syllables; 3) an instruction issue unit for receiving fetched ones of the plurality of cache lines and issuing complete instruction bundles toward the C execution clusters; and 4) alignment and dispersal circuitry for receiving the complete instruction bundles from the instruction issue unit and routing each the received complete instruction bundles to a correct one of the C execution clusters as a function of at least one address bit associated with each of the complete instruction bundles.

摘要翻译： 公开了用于数据处理器的束对准和分散电路。 数据处理器包括：1）C个执行群集，每个C个执行群集包括具有N个处理阶段的指令执行流水线，用于执行包括从1到S个音节的指令包，其中每个指令执行流水线是L个通道宽度， 用于接收指令集的一个到S个音节中的一个的L个通道; 2）用于存储多个高速缓存行的指令高速缓存，每个高速缓存行包括C * L音节; 3）指令发布单元，用于接收所述多个高速缓存行中的获取的高速缓存行，并向所述C个执行集群发布完整的指令集; 以及4）对准和分散电路，用于接收来自指令发布单元的完整指令集并且根据与每个完整指令集相关联的至少一个地址位将每个接收到的完整指令集路由到C个执行集群中的正确的一个C执行集群 指令包。

公开(公告)号：EP1220089A3

公开(公告)日：2002-11-13

申请号：EP01310643.0

申请日：2001-12-19

申请人： STMicroelectronics, Inc.

发明人： Homewood, Mark Owen ,  Vondran, Gary L. ,  Brown, Geoffrey M. ,  Faraboschi, Paolo

IPC分类号： G06F9/32 ,  G06F9/38

CPC分类号： G06F9/30058 ,  G06F9/3885

摘要： There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address, (ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The- data processor then uses the computed branch condition to select one of the branch address or the next program counter address.