中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.01 seconds)

    METHOD AND APPARATUS FOR IN-MEMORY CONVOLUTIONAL COMPUTATION
    1.
    发明公开
    METHOD AND APPARATUS FOR IN-MEMORY CONVOLUTIONAL COMPUTATION 审中-公开

    公开(公告)号：EP3955169A1

    公开(公告)日：2022-02-16

    申请号：EP21186854.2

    申请日：2021-07-21

    Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics S.r.l.

    Inventor： LA ROSA, Francesco ,  CONTE, Antonino

    IPC: G06N3/063 ,  G06F17/16 ,  G11C11/54 ,  G11C11/56

    Abstract: The method for convolutional computation (CNVL) comprises programming floating gate transistors (FGT) belonging to non-volatile memory cells (NVM) to multilevel threshold voltages (MLTLVL) according to weight factors (W11-Wnm) of a convolutional matrix operator (MTXOP). The computation comprises performing a multiply and accumulate sequence (MACi) during a sensing operation (SNS) of memory cells (NVMij), the time (T) elapsed for each memory cell to become conductive in response to a voltage ramp control signal (VRMP) providing the value of each product of input values (A1 ... An) by a respective weight factor (Wi1 ... Win), the values of the products being accumulated to corresponding output values (Bi).

    SENSE-AMPLIFIER CIRCUIT WITH OFFSET COMPENSATION FOR A NON-VOLATILE MEMORY DEVICE
    2.
    发明授权
    SENSE-AMPLIFIER CIRCUIT WITH OFFSET COMPENSATION FOR A NON-VOLATILE MEMORY DEVICE 有权

    公开(公告)号：EP3174200B1

    公开(公告)日：2018-08-22

    申请号：EP16170438.2

    申请日：2016-05-19

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

    Inventor： CONTE, Antonino ,  LA ROSA, Francesco

    IPC: H03F3/45

    CPC classification number: G11C7/08 ,  G11C7/062 ,  G11C7/12 ,  G11C16/28 ,  H03F3/45475 ,  H03F3/45968 ,  H03F2203/45212

    Abstract: A sense-amplifier circuit (10) of a non-volatile memory device (1), provided with: a biasing stage (11), which biases a bitline (BL) of a memory array (2) for pre-charging it during a pre-charging step of a reading operation of a datum stored in a memory cell (3); a current-to-voltage converter stage (12), with differential configuration and a first circuit branch (12a) and a second circuit branch (12b), which receive on a respective comparison input (IN a , IN b ), during a reading step of the datum subsequent to the pre-charging step, a cell current (I cell ) and a reference current (I ref ), each having a respective amplification module (22a, 22b), which generates a respective amplified voltage (V a , V b ), an output voltage (V out ) being a function of the difference between the amplified voltages (V a , V b ) and indicative of the value of the datum. A capacitive compensation module (26) detects and stores an offset between the first and second circuit branches during the pre-charging step, and compensates this offset in the output voltage (V out ) during the reading step of the datum.

    TESTING CIRCUIT OF A LONG-TIME-CONSTANT CIRCUIT STAGE AND CORRESPONDING TESTING METHOD
    5.
    发明公开
    TESTING CIRCUIT OF A LONG-TIME-CONSTANT CIRCUIT STAGE AND CORRESPONDING TESTING METHOD 审中-公开
    长时间恒定电路的测试电路及相应的测试方法

    公开(公告)号：EP3264201A1

    公开(公告)日：2018-01-03

    申请号：EP16206890.2

    申请日：2016-12-23

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

    Inventor： CONTE, Antonino ,  CASTALDO, Enrico ,  BIANCHI, Raul Andres ,  LA ROSA, Francesco

    IPC: G04F10/10

    CPC classification number: G01R31/028 ,  G01R31/2882 ,  G04F10/10

    Abstract: A testing circuit (19) for a charge-retention circuit stage (1) for measurement of a time interval provided with: a storage capacitor (2) connected between a first biasing terminal (3a) and a floating node (4); and a discharge element (6) connected between the floating node and a reference terminal (7), for discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The testing circuit envisages: a biasing stage (24) for biasing the floating node at a reading voltage (V L ); a detection stage (30, 32) for detecting the biasing value (V L (t 0 )) of the reading voltage; and an integrator stage (20), having a test capacitor (28) coupled to the floating node, for implementing an operation of integration of the discharge current (i L ) in the discharge element with the reading voltage kept constant at the biasing value, and determining an effective resistance value (R L ') of the discharge element as a function of the integration operation.

    Abstract translation: 一种用于测量时间间隔的电荷保持电路级（1）的测试电路（19），其具有：连接在第一偏置端子（3a）和浮动节点（4）之间的存储电容器（2）; 以及连接在浮置节点和参考端子（7）之间的放电元件（6），用于通过相应的电介质泄漏存储在存储电容器中的电荷。 测试电路设想：用于将浮置节点偏置在读取电压（VL）的偏置级（24）; 检测级（30,32），用于检测读取电压的偏置值（VL（t0））; 和具有耦合到浮动节点的测试电容器（28）的积分器级（20），用于实现放电元件中放电电流（iL）的积分操作，其中读取电压保持恒定在偏置值，以及 根据积分操作确定排出元件的有效电阻值（RL'）。

    METHOD FOR IN-MEMORY CONVOLUTIONAL COMPUTATION AND CORRESPONDING INTEGRATED CIRCUIT
    6.
    发明公开
    METHOD FOR IN-MEMORY CONVOLUTIONAL COMPUTATION AND CORRESPONDING INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：EP3955171A1

    公开(公告)日：2022-02-16

    申请号：EP21189279.9

    申请日：2021-08-03

    Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics S.r.l.

    Inventor： conte, Antonino ,  LA ROSA, Francesco

    IPC: G06N3/063 ,  G06N3/04 ,  G11C13/00

    Abstract: The integrated circuit for convolutional computation (CNVL) comprises an array (ARR) of non-volatile memory points (MPT ij ) each comprising a phase-change resistive memory cell (PCM ij ) coupled with a bit line (BL j ), and a selection bipolar transistor (BJT ij ) coupled in series with the cell and having a base terminal coupled with a word line (WL i ), an input converter circuit (INCVRT) configured to receive and convert input values (A 1 -A 4 ) to voltage signals (V 1 -V 4 ) and to successively apply the voltage signals (V 1 -V 4 ) on selected bit lines (BL 1 -BL 4 ) over respective time slots (t1-t4), and an output converter circuit (OUTCVRT) configured to integrate over the successive time slots (t1-t4) the read currents (I WL ) resulting from the voltage signals (V 1 -V 4 ) biasing the respective phase-change resistive memory cells (PCM ij ) and flowing through selected word lines, and to convert the integrated read currents (I WL ) to outputs values (B i ).

    SENSE-AMPLIFIER CIRCUIT WITH OFFSET COMPENSATION FOR A NON-VOLATILE MEMORY DEVICE
    9.
    发明公开
    SENSE-AMPLIFIER CIRCUIT WITH OFFSET COMPENSATION FOR A NON-VOLATILE MEMORY DEVICE 审中-公开
    用于非易失性存储器设备的具有失调补偿的检测放大器电路

    公开(公告)号：EP3174200A1

    公开(公告)日：2017-05-31

    申请号：EP16170438.2

    申请日：2016-05-19

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

    Inventor： CONTE, Antonino ,  LA ROSA, Francesco

    IPC: H03F3/45

    CPC classification number: G11C7/08 ,  G11C7/062 ,  G11C7/12 ,  G11C16/28 ,  H03F3/45475 ,  H03F3/45968 ,  H03F2203/45212

    Abstract: A sense-amplifier circuit (10) of a non-volatile memory device (1), provided with: a biasing stage (11), which biases a bitline (BL) of a memory array (2) for pre-charging it during a pre-charging step of a reading operation of a datum stored in a memory cell (3); a current-to-voltage converter stage (12), with differential configuration and a first circuit branch (12a) and a second circuit branch (12b), which receive on a respective comparison input (IN a , IN b ), during a reading step of the datum subsequent to the pre-charging step, a cell current (I cell ) and a reference current (I ref ), each having a respective amplification module (22a, 22b), which generates a respective amplified voltage (V a , V b ), an output voltage (V out ) being a function of the difference between the amplified voltages (V a , V b ) and indicative of the value of the datum. A capacitive compensation module (26) detects and stores an offset between the first and second circuit branches during the pre-charging step, and compensates this offset in the output voltage (V out ) during the reading step of the datum.

    Abstract translation: 一种非易失性存储器件（1）的读出放大器电路（10），其设置有：偏置级（11），其偏置存储器阵列（2）的位线（BL） 对存储在存储单元（3）中的数据进行读取操作的预充电步骤; 具有差分配置的电流至电压转换器级（12）和第一电路分支（12a）和第二电路分支（12b），其在相应的比较输入（INa，INb） 在预充电步骤之后的数据，电池电流（Icell）和参考电流（Iref），每个电池具有各自的放大模块（22a，22b），其产生各自的放大电压（Va，Vb），输出 电压（Vout）是放大电压（Va，Vb）之间的差值以及指示数据值的函数。 电容补偿模块（26）在预充电步骤期间检测并存储第一和第二电路支路之间的偏移，并在数据的读取步骤期间补偿输出电压（Vout）中的该偏移。

    READING CIRCUIT FOR A LONG-TIME-CONSTANT CIRCUIT STAGE AND CORRESPONDING READING METHOD
    10.
    发明公开
    READING CIRCUIT FOR A LONG-TIME-CONSTANT CIRCUIT STAGE AND CORRESPONDING READING METHOD 审中-公开
    长时间恒定电路的读取电路及相应的读取方法

    公开(公告)号：EP3264202A1

    公开(公告)日：2018-01-03

    申请号：EP16206892.8

    申请日：2016-12-23

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

    Inventor： CONTE, Antonino ,  CASTALDO, Enrico ,  BIANCHI, Raul Andres ,  LA ROSA, Francesco

    IPC: G04F10/10

    CPC classification number: G11C11/24 ,  G04F10/10

    Abstract: A reading circuit (19) for a charge-retention circuit stage (1) provided with: a storage capacitor (2) connected between a first biasing terminal (3a) and a floating node (4); and a discharge element (6) connected between the floating node and a reference terminal (7), for discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The reading circuit further has: an operational amplifier (20) having a first input terminal (20a), which is connected to the floating node and receives a reading voltage (V L ), a second input terminal (20b), which receives a reference voltage (V x ), and an output terminal (20c) on which it supplies an output voltage (V out ), the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage (24, 26) shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.

    Abstract translation: 一种用于电荷保持电路级（1）的读取电路（19），其设置有：存储电容器（2），其连接在第一偏置端子（3a）和浮置节点（4）之间; 以及连接在浮置节点和参考端子（7）之间的放电元件（6），用于通过相应的电介质泄漏存储在存储电容器中的电荷。 所述读取电路还具有：运算放大器（20），其具有连接到所述浮动节点并接收读取电压（VL）的第一输入端子（20a）;第二输入端子（20b），其接收参考电压 （Vx）以及其上提供输出电压（Vout）的输出端子（20c），该输出电压的值是读取电压和参考电压之间的比较以及指示存储电容器中的剩余电荷的函数 。 在比较读取电压和用于提供输出电压的参考电压之前，移位级（24,26）移动浮动节点的读取电压的值。

Patent Agency Ranking