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公开(公告)号:EP4401323A1
公开(公告)日:2024-07-17
申请号:EP23219526.3
申请日:2023-12-21
CPC分类号: H04B1/16 , H04B1/30 , H04L27/02 , H03M1/0607
摘要: A receiver circuit for use, for instance, in interchip data communication in the automotive sector comprises an envelope detector (M1, M2, RL1, CED) configured to receive (RX1) an on-off keying, OOK signal modulated over a RF carrier. A differential stage (121, 122, RL2) has a first input (VA) coupled to the envelope detector (M1, M2, RL1, CED) and a second input (VB) configured to receive a reference signal. A comparator (16) is coupled (14) to first (C) and second (D) output nodes of the differential stage (121, 122, RL2) produces a PWM-modulated signal (PWMOUT) having on and off times. Offset compensation circuitry comprises a first switch (S1,Φ1) to short-circuit the input to the envelope detector (M1, M2, RL1, CED), a storage capacitor (CH) coupled to the second input (VB) of the differential stage (121, 122, RL2) and a second switch (S1,Φ2) to feed back to the storage capacitor (CH) a signal (18) indicative of the difference between the first (C) and the second (D) output nodes of the differential stage (121, 122, RL2), and a third switch (S3,Φ1) to short-circuit the input to the comparator (16) . Logic circuitry (100) activates the offset compensation circuitry in a sequence of phases comprising a start-up phase (SUP) and at least one standby phase (STBY) wherein the first (S1,Φ1), second (S2,Φ2) and third (S3,Φ1) switches are made conductive in the absence of the PWM-modulated signal (PWMOUT), and a working phase (WP) alternating with the start-up phase (SUP) or the at least one standby phase (STBY) in the presence of the PWM-modulated signal (PWMOUT) wherein the first (S1,Φ1), second (S2,Φ2) and third (S3,Φ1) switches are made conductive during off times (T2) of the PWM-modulated signal (PWMOUT).