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1.发明公开Circuitry and a method for introducing a delay 有权Schaltung und Verfahren zurEinführungeinerVerzögerung
公开(公告)号：EP1014579A2
公开(公告)日：2000-06-28
申请号：EP99310156.7
申请日：1999-12-16
发明人： Barnes, William
IPC分类号： H03K5/13
CPC分类号： H03K5/131 , H03L7/0812
摘要： Circuitry for introducing a delay to a signal comprising input means for receiving the signal to be delayed; a first delay path; a second delay path; selection means for causing the signal passing through a selected one of the delay paths to be output from said circuitry; comparing means for comparing the phase difference between the signal output by said circuitry and the input to said selected delay path to provide a first comparison signal and for comparing the phase delay of said first delay path with that of said second delay path to provide a second comparison signal, wherein said first and second comparison signals are used by the selection means to determine which of said delay paths is selected.
摘要翻译： 用于对包括用于接收要延迟的信号的输入装置的信号引入延迟的电路; 第一延迟路径; 第二延迟路径; 选择装置，用于使从所述电路输出通过选定的一个所述延迟路径的信号; 比较装置，用于比较由所述电路输出的信号与所述选择的延迟路径的输入之间的相位差，以提供第一比较信号，并用于将所述第一延迟路径的相位延迟与所述第二延迟路径的相位延迟进行比较，以提供第二 比较信号，其中所述第一和第二比较信号由所述选择装置用于确定哪个所述延迟路径被选择。
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公开(公告)号：EP1255253A1
公开(公告)日：2002-11-06
申请号：EP01303380.8
申请日：2001-04-11
发明人： Barnes, William
IPC分类号： G11C8/00 , G11C11/412
CPC分类号： G11C11/412
摘要： A dual port memory cell has a latch portion for holding data, first and second write transistors and first and second read transistors. The read transistors each have a control gate connected to the latch portion of the cell and a read enable terminal, wherein the read enable terminals are connected at a common read enable node to which the enabling signal is applied. This differs from existing cells in that the drive from the latch portion is through the gate of the read transistors rather than via the source/drain channels. Thus a larger size for the read transistors can be used without affecting cell stability.
摘要翻译： 双端口存储单元具有用于保持数据的锁存部分，第一和第二写入晶体管以及第一和第二读取晶体管。 读取晶体管各自具有连接到单元的锁存部分的控制栅极和读取使能端子，其中读取使能端子在施加使能信号的公共读取使能节点处连接。 这与现有单元的不同之处在于，来自锁存部分的驱动是通过读取晶体管的栅极而不是通过源极/漏极通道。 因此可以使用读取晶体管的较大尺寸而不影响电池稳定性。
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公开(公告)号：EP1014579A3
公开(公告)日：2001-08-08
申请号：EP99310156.7
申请日：1999-12-16
发明人： Barnes, William
CPC分类号： H03K5/131 , H03L7/0812
摘要： Circuitry for introducing a delay to a signal comprising input means for receiving the signal to be delayed; a first delay path; a second delay path; selection means for causing the signal passing through a selected one of the delay paths to be output from said circuitry; comparing means for comparing the phase difference between the signal output by said circuitry and the input to said selected delay path to provide a first comparison signal and for comparing the phase delay of said first delay path with that of said second delay path to provide a second comparison signal, wherein said first and second comparison signals are used by the selection means to determine which of said delay paths is selected.
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公开(公告)号：EP1014579B1
公开(公告)日：2005-10-05
申请号：EP99310156.7
申请日：1999-12-16
发明人： Barnes, William
CPC分类号： H03K5/131 , H03L7/0812
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6.发明公开Built-in test circuit and method for an integrated circuit 审中-公开Eingebaute Testschaltung und -verfahren在einer integrierten Schaltung
公开(公告)号：EP1231608A1
公开(公告)日：2002-08-14
申请号：EP01301092.1
申请日：2001-02-07
发明人： Firth, Steven , Barnes, William
IPC分类号： G11C29/00
摘要： Test circuitry for testing an integrated circuit, the integrated circuit being configurable to accept input data from stimulus scan cells and to provide output data to response scan cells, the test circuitry including stimulus circuitry for providing test data to the integrated circuit; input selection means operable to control which of the test data and the input data are received at the integrated circuit; capture circuitry for capturing output data from the integrated circuit and generating response data; output selection means operable to select which of the output data and the response data are received by the response scan cells.
摘要翻译： 用于测试集成电路的测试电路，所述集成电路可配置为接受来自激励扫描单元的输入数据，并向响应扫描单元提供输出数据，所述测试电路包括用于向所述集成电路提供测试数据的激励电路; 输入选择装置，用于控制在集成电路处接收的测试数据和输入数据中的哪一个; 用于从集成电路捕获输出数据并产生响应数据的捕获电路; 输出选择装置，用于选择响应扫描单元接收哪一个输出数据和响应数据。
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