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    Antifuse reroute of dies
    2.
    发明公开
    Antifuse reroute of dies 审中-公开
    信号与反熔丝芯片重新路由

    公开(公告)号：EP2285002A3

    公开(公告)日：2014-07-09

    申请号：EP10186003.9

    申请日：2002-03-15

    申请人： Micron Technology, Inc.

    发明人： Duesman, Kevin

    IPC分类号： H03K19/173 ,  G11C5/06 ,  G11C29/00 ,  G11C29/48 ,  H01L23/525 ,  H03K17/693

    CPC分类号： H03K19/1736 ,  G11C5/06 ,  G11C29/48 ,  H01L23/525 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03K17/693 ,  H01L2924/00

    摘要： A semiconductor die is provided with an internally programmable router to assign signal paths to select connection points. A switching matrix incorporating at least one antifuse is utilized to selectively route signal paths on the semiconductor die. The chips can then be used individually, for example to reconfigure chip pin assignments to operate in a plurality of different socket layouts, or where features or controls of a chip are selectively enabled or disabled. A further alternative involves programming a first chip, then stacking piggyback, or one on top of the other, the first chip onto a second chip. The contact pins are electrically coupled together, thus avoiding the need for external frames and pin rerouting schemes to form stacked chips. In the stacked chip configuration, control pins are rerouted to align with unused pins on the chip stacked against.

    Antifuse reroute of dies
    3.
    发明公开
    Antifuse reroute of dies 审中-公开
    信号在IC与反熔丝重路由

    公开(公告)号：EP2088675A3

    公开(公告)日：2014-07-09

    申请号：EP09160308.4

    申请日：2002-03-15

    申请人： Micron Technology, Inc.

    发明人： Duesman, Kevin

    IPC分类号： H03K19/173 ,  G11C5/06 ,  G11C29/00 ,  G11C29/48 ,  H01L23/525 ,  H03K17/693

    CPC分类号： H03K19/1736 ,  G11C5/06 ,  G11C29/48 ,  H01L23/525 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03K17/693 ,  H01L2924/00

    摘要： A semiconductor die is provided with an internally programmable router to assign signal paths to select connection points. A switching matrix incorporating at least one antifuse is utilized to selectively route signal paths on the semiconductor die. The chips can then be used individually, for example to reconfigure chip pin assignments to operate in a plurality of different socket layouts, or where features or controls of a chip are selectively enabled or disabled. A further alternative involves programming a first chip, then stacking piggyback, or one on top of the other, the first chip onto a second chip. The contact pins are electrically coupled together, thus avoiding the need for external frames and pin rerouting schemes to form stacked chips. In the stacked chip configuration, control pins are rerouted to align with unused pins on the chip stacked against.

    Semiconductor device
    4.
    发明公开
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号：EP2533277A2

    公开(公告)日：2012-12-12

    申请号：EP12170813.5

    申请日：2012-06-05

    申请人： Elpida Memory, Inc.

    发明人： Ishikawa, Toru

    IPC分类号： H01L21/66 ,  H01L23/48

    CPC分类号： G11C7/1057 ,  G01R31/2884 ,  G11C5/04 ,  G11C7/1051 ,  G11C29/1201 ,  G11C29/48 ,  H01L22/34 ,  H01L23/481 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

    摘要： A device includes a semiconductor substrate, a first penetrating electrode (TSV_0) penetrating through the semiconductor substrate, a first test pad (PAD_0), and a first tri-state buffer (TD_0) coupled between the first penetrating electrode and the first test pad. The first tri-state buffer receives a buffer control signal at a control terminal thereof. The device further includes a buffer control circuit (BC) supplying the buffer control signal to the first tri-state buffer.

    摘要翻译： 一种器件包括半导体衬底，穿透半导体衬底的第一穿透电极（TSV_0），第一测试焊盘（PAD_0）和耦合在第一穿透电极和第一测试焊盘之间的第一三态缓冲器（TD_0）。 第一三态缓冲器在其控制端接收缓冲控制信号。 该装置还包括将缓冲控制信号提供给第一三态缓冲器的缓冲器控制电路（BC）。

    Method and device for testing memory
    5.
    发明公开
    Method and device for testing memory 有权
    Verfahren und Vorrichtung zumPrüfeneines Speichers

    公开(公告)号：EP2421004A1

    公开(公告)日：2012-02-22

    申请号：EP11188850.9

    申请日：2007-12-14

    申请人： Qualcomm Incorporated

    发明人： Shen, Jian ,  Bassett, Paul

    IPC分类号： G11C29/48

    CPC分类号： G11C29/48 ,  G11C29/1201

    摘要： A method is disclosed, the method comprising initiating a test on a computer readable memory comprising a first input and a first output, the computer readable memory providing output data associated with the test; selecting to receive the output data from one of a first register and a second register the first register comprising a second input and a second output, the second output coupled to the first input of the computer readable memory, and the second register comprising a third input and a third output, the third input coupled to the first output of the computer readable memory; receiving data during a write operation at a first input of a first multiplexer, the first multiplexer comprising a fourth output coupled to the second input of the first register; and receiving data during a test mode write operation at a second input of the first multiplexer, wherein a third input of the first multiplexer is coupled to the first output of the computer readable memory.

    摘要翻译： 公开了一种方法，所述方法包括在包括第一输入和第一输出的计算机可读存储器上启动测试，所述计算机可读存储器提供与所述测试相关联的输出数据; 选择从第一寄存器和第二寄存器之一接收输出数据，第一寄存器包括第二输入和第二输出，第二输出耦合到计算机可读存储器的第一输入，第二寄存器包括第三输入 和第三输出，所述第三输入耦合到所述计算机可读存储器的所述第一输出; 在第一多路复用器的第一输入处的写操作期间接收数据，第一多路复用器包括耦合到第一寄存器的第二输入的第四输出; 以及在所述第一多路复用器的第二输入处的测试模式写入操作期间接收数据，其中所述第一多路复用器的第三输入耦合到所述计算机可读存储器的第一输出。

    PROGRAMMABLE MEMORY REPAIR SCHEME
    6.
    发明公开
    PROGRAMMABLE MEMORY REPAIR SCHEME 审中-公开
    REPARATURSCHEMAFÜRPROGRAMMIBAREN SPEICHER

    公开(公告)号：EP2301038A1

    公开(公告)日：2011-03-30

    申请号：EP09730954.6

    申请日：2009-04-09

    申请人： Rambus Inc.

    发明人： ONG, Adrian, E. ,  HO, Fan

    IPC分类号： G11C29/00

    CPC分类号： G11C29/76 ,  G11C11/401 ,  G11C11/4085 ,  G11C29/027 ,  G11C29/04 ,  G11C29/12 ,  G11C29/4401 ,  G11C29/48 ,  G11C29/78 ,  G11C29/789 ,  G11C29/802 ,  G11C2229/743

    摘要： The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elements and one or more redundant data storage elements, the primary data storage elements having respective addresses for memory access operations. The repair circuit is programmable by another semiconductor device separate from the memory device to recognize a malfunctioning address of the primary data storage elements and the programmed repair circuit is configured to reroute memory access from a primary data storage element having the recognized malfunctioning address to a corresponding redundant data storage element.

    摘要翻译： 本公开提供了用于测试和操作该半导体器件的方法，系统和装置。 半导体存储器件包括数据存储元件和修复电路。 数据存储元件包括主数据存储元件和一个或多个冗余数据存储元件，主数据存储元件具有用于存储器访问操作的相应地址。 修复电路可以由与存储器件分离的另一个半导体器件编程，以识别主数据存储元件的故障地址，并且编程的修复电路被配置为将具有识别的故障地址的主数据存储元件的存储器访问重新路由到相应的 冗余数据存储元件。

    Antifuse reroute of dies
    8.
    发明公开
    Antifuse reroute of dies 审中-公开
    Umleitung von Signalen auf ic's mit Antischmelzsicherungen

    公开(公告)号：EP2088675A2

    公开(公告)日：2009-08-12

    申请号：EP09160308.4

    申请日：2002-03-15

    申请人： Micron Technology, Inc.

    发明人： Duesman, Kevin

    IPC分类号： H03K19/173 ,  G11C5/06 ,  G11C29/00

    CPC分类号： H03K19/1736 ,  G11C5/06 ,  G11C29/48 ,  H01L23/525 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03K17/693 ,  H01L2924/00

    摘要： A semiconductor die is provided with an internally programmable router to assign signal paths to select connection points. A switching matrix incorporating at least one antifuse is utilized to selectively route signal paths on the semiconductor die. The chips can then be used individually, for example to reconfigure chip pin assignments to operate in a plurality of different socket layouts, or where features or controls of a chip are selectively enabled or disabled. A further alternative involves programming a first chip, then stacking piggyback, or one on top of the other, the first chip onto a second chip. The contact pins are electrically coupled together, thus avoiding the need for external frames and pin rerouting schemes to form stacked chips. In the stacked chip configuration, control pins are rerouted to align with unused pins on the chip stacked against.

    摘要翻译： 半导体管芯具有内部可编程的路由器以分配信号路径以选择连接点。 采用包含至少一个反熔丝的开关矩阵来选择性地路由半导体管芯上的信号路径。 然后，可以单独使用芯片，例如重新配置芯片引脚分配以在多个不同的插座布局中操作，或者芯片的特征或控制被选择性地启用或禁用。 另一个替代方案涉及对第一芯片进行编程，然后将第一芯片堆叠到另一芯片上，或者将第一芯片堆叠在另一芯片上。 接触引脚电耦合在一起，因此避免了外部框架和引脚重新布线方案的需要以形成堆叠的芯片。 在堆叠芯片配置中，控制引脚被重新路由以与堆叠的芯片上的未使用的引脚对齐。

    Compressing test responses using a compactor
    9.
    发明公开
    Compressing test responses using a compactor 有权
    Komprimieren von Testantworten unter Verwendung eines Kompaktors

    公开(公告)号：EP1978446A1

    公开(公告)日：2008-10-08

    申请号：EP08159782.5

    申请日：2004-02-13

    申请人： Mentor Graphics Corporation

    发明人： Rajski, Janusz ,  Tyszer, Jerzy ,  Wang, Chen ,  Mrugalski, Grzegorz ,  Pogiel, Artur

    IPC分类号： G06F11/00 ,  G01R31/3185

    CPC分类号： G01R31/318566 ,  G01R31/31703 ,  G01R31/318536 ,  G01R31/318583 ,  G01R31/31921 ,  G11C29/40 ,  G11C29/48 ,  G11C2029/3202

    摘要： A method for testing an integrated circuit, comprising:
    capturing multiple test values in scan chains of a circuit-under-test, the test values being associated with a circuit response to a test pattern;
    clocking the test values out of the scan chains and into a compactor;
    producing sets of two or more output values in the compactor, each set comprising all values produced in the compactor at least partially determined by a respective test value; and
    outputting at least one of the sets from the compactor over at least two clock cycles and before all of the test values captured in the scan chain and associated with the circuit response to the test pattern have been clocked into the compactor.

    摘要翻译： 一种用于测试集成电路的方法，包括：在被测电路的扫描链中捕获多个测试值，所述测试值与对测试图案的电路响应相关联; 将测试值从扫描链中计时并输入压实器; 在压实机中产生两个或更多个输出值的组，每组包括至少部分地由相应测试值确定的在压实机中产生的所有值; 并且在至少两个时钟周期之后以及在扫描链中捕获的所有测试值和与测试图案的电路响应相关联的所有测试值已被计时到压缩机中之前，从压实机输出至少一个组。