公开(公告)号：EP4280215A3

公开(公告)日：2023-12-06

申请号：EP23164276.0

申请日：2023-03-27

Applicant: STMicroelectronics S.r.l.

Inventor： GIRARDI, Walter

IPC: G11C29/12 ,  G11C29/48 ,  G11C29/14

Abstract: A circuit (500) for reading or writing a random access memory, RAM (502) comprises:
a shift register (508) coupled to the RAM (502), a test data input (504), and a test data output (506); and
a control circuit (510) configured to generate a pulse every N clock cycles, each pulse triggering a RAM access operation transferring data between the shift register and the RAM (502), N being equal to a data width of the RAM divided by a parallel factor, the parallel factor being a number of pins in either the test data input or the test data output configured for parallel data loading.

公开(公告)号：EP4280215A2

公开(公告)日：2023-11-22

申请号：EP23164276.0

申请日：2023-03-27

Applicant: STMicroelectronics S.r.l.

Inventor： GIRARDI, Walter

IPC: G11C29/14 ,  G11C29/48

Abstract: A circuit (500) for reading or writing a random access memory, RAM (502) comprises:
a shift register (508) coupled to the RAM (502), a test data input (504), and a test data output (506); and
a control circuit (510) configured to generate a pulse every N clock cycles, each pulse triggering a RAM access operation transferring data between the shift register and the RAM (502), N being equal to a data width of the RAM divided by a parallel factor, the parallel factor being a number of pins in either the test data input or the test data output configured for parallel data loading.