Bus architecture for integrated data and video memory
    1.
    发明公开
    Bus architecture for integrated data and video memory 失效
    Busarchitekturfürintegrierten Daten / - und Videospeicher。

    公开(公告)号:EP0571099A1

    公开(公告)日:1993-11-24

    申请号:EP93303452.2

    申请日:1993-05-04

    CPC分类号: G06F13/4243 G06F13/1663

    摘要: A bus architecture and protocol for integrated data and video memory. A high speed dedicated memory bus is coupled to a memory controller. The memory controller is in turn coupled to a multiple processor bus interconnecting one or more processors. Single in-line memory modules (SIMMs) incorporating dynamic random access memory (DRAM), video RAM (VRAM), and static nonvolatile RAM (SRAM) are coupled to the memory bus. Bus control signals forming a bus protocol, and address and data lines from the memory controller are shared by all memory modules operating on the memory bus. Certain control signals invoke specific operations on memory modules or are ignored, depending on the type of memory module receiving the control signal. The memory modules incorporate the consistent protocol by virtue of a consistent control signal pin out. The SIMMs further incorporate buffering and conversion functions, thereby relieving the memory controller of service overhead associated with these functions. Integrating all forms of memory into a single data and video memory architecture permits a highly functional dedicated memory bus to be connected to the computer system.

    摘要翻译: 用于集成数据和视频存储器的总线架构和协议。 高速专用存储器总线耦合到存储器控制器。 存储器控制器又耦合到互连一个或多个处理器的多处理器总线。 结合动态随机存取存储器(DRAM),视频RAM(VRAM)和静态非易失性RAM(SRAM)的单列直插存储器模块(SIMM)耦合到存储器总线。 形成总线协议的总线控制信号,以及来自存储器控制器的地址和数据线由在存储器总线上操作的所有存储器模块共享。 某些控制信号根据接收控制信号的存储器模块的类型,调用对存储器模块的特定操作或被忽略。 存储器模块通过一致的控制信号引脚引入一致的协议。 SIMM还包括缓冲和转换功能,从而减轻存储器控制器与这些功能相关联的业务开销。 将所有形式的存储器集成到单个数据和视频存储器架构中,允许将高度功能的专用存储器总线连接到计算机系统。