公开(公告)号：EP4411537A1

公开(公告)日：2024-08-07

申请号：EP24155338.7

申请日：2024-02-01

申请人： Samsung Electronics Co., Ltd.

发明人： SIM, Hyunwoo ,  KIM, Hyunpil ,  AHN, Seongwoo

IPC分类号： G06F9/30 ,  G06F9/46

CPC分类号： G06F9/462 ,  G06F9/30116 ,  G06F9/3013 ,  G06F9/30101

摘要： A processor includes a register file, a context controller that, in response to a target interrupt occurring, is configured to determine, a target register that stores new data acquired through each of commands for executing an interrupt service routine (ISR) among the plurality of registers, a write buffer configured to transmit pre-data stored in the target register to a memory, and a flag register configured to store set data including set values indicating whether the new data is stored in each of the registers. The context controller is configured to determine whether to transfer the pre-data to the memory through the write buffer based on the set data.