公开(公告)号：EP3992968A1

公开(公告)日：2022-05-04

申请号：EP21187134.8

申请日：2021-07-22

申请人： Samsung Electronics Co., Ltd.

发明人： PARK, Jun Young ,  SON, Young-Hoon ,  CHO, Hyun-Yoon ,  CHOI, Young Don ,  CHOI, Jung Hwan

IPC分类号： G11C7/22 ,  G11C29/02 ,  G11C7/10

摘要： A memory device includes a multiphase clock generator which generates a plurality of divided clock signals, a first error correction block which receives a first divided clock signal among the plurality of divided clock signals, a first data multiplexer which transmits first least significant bit data corresponding to the first divided clock signal, a second error correction block which receives the first divided clock signal, and a second data multiplexer which transmits first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a toggle timing of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a toggle time of the first most significant bit data.