公开(公告)号：EP3992968A1

公开(公告)日：2022-05-04

申请号：EP21187134.8

申请日：2021-07-22

申请人： Samsung Electronics Co., Ltd.

发明人： PARK, Jun Young ,  SON, Young-Hoon ,  CHO, Hyun-Yoon ,  CHOI, Young Don ,  CHOI, Jung Hwan

IPC分类号： G11C7/22 ,  G11C29/02 ,  G11C7/10

摘要： A memory device includes a multiphase clock generator which generates a plurality of divided clock signals, a first error correction block which receives a first divided clock signal among the plurality of divided clock signals, a first data multiplexer which transmits first least significant bit data corresponding to the first divided clock signal, a second error correction block which receives the first divided clock signal, and a second data multiplexer which transmits first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a toggle timing of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a toggle time of the first most significant bit data.

公开(公告)号：EP4177889A1

公开(公告)日：2023-05-10

申请号：EP22184408.7

申请日：2022-07-12

申请人： Samsung Electronics Co., Ltd.

发明人： KIM, Joo Hwan ,  LEE, Su Cheol ,  BYUN, Jin Do ,  SHIN, Eun Seok ,  CHOI, Young Don ,  CHOI, Jung Hwan

IPC分类号： G11C7/10

摘要： A memory device, a host device and a method of operating the memory device are provided. The memory device includes a data signal generator configured to provide a data signal to a transmission driver, the transmission driver configured to output a multi-level signal having any one of first to third signal levels based on the data signal, a command decoder configured to receive a feedback signal from outside of the memory device and decode the feedback signal, a data signal controller configured to adjust the data signal based on a decoding result of the command decoder, and a drive strength controller configured to adjust at least one of the first to third signal levels based on the decoding result of the command decoder.

公开(公告)号：EP4002465A1

公开(公告)日：2022-05-25

申请号：EP21201840.2

申请日：2021-10-11

申请人： Samsung Electronics Co., Ltd.

发明人： LEE, Min Jae ,  BYUN, Jin Do ,  SON, Young-Hoon ,  CHOI, Young Don ,  KWAK, Pan Suk ,  LEE, Myung Hun ,  CHOI, Jung Hwan

IPC分类号： H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L23/48 ,  H01L23/00 ,  H01L27/11565 ,  H01L25/065

摘要： A non-volatile memory chip comprises a cell region that includes a first surface, a second surface opposite to the first surface, a first cell structure, and a second cell structure spaced apart from the first cell structure; a peripheral circuit region on the first surface of the cell region, and that includes a first peripheral circuit connected to the first cell structure, a second peripheral circuit connected to the second cell structure, and a connection circuit between the first and second peripheral circuits; a through via between the first and second cell structures and that extends from the second surface of the cell region to the connection circuit of the peripheral circuit region; a redistribution layer that covers the through via on the second surface of the cell region, is connected to the through via, and extends along the second surface; and a chip pad connected to the redistribution layer.