公开(公告)号：EP4365949A1

公开(公告)日：2024-05-08

申请号：EP23207187.8

申请日：2023-10-31

申请人： Samsung Electronics Co., Ltd.

发明人： KIM, Gukhee ,  LEE, Kyoungwoo ,  NA, Sangcheol ,  GWAK, Minchan ,  KIM, Youngwoo ,  KIM, Hojun ,  LEE, Dongick

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823412 ,  H01L21/76898 ,  H01L23/481

摘要： An embodiment of the present inventive concept provides a semiconductor device, comprising: first and second fin-type active patterns disposed on an upper surface of a substrate, and having different widths; first and second gate structures crossing the first and second fin-type active patterns, respectively; first and second source/drain regions disposed on the first and second fin-type active patterns, respectively; first and second contact structures connected to the first and second source/drain regions, respectively; a gate isolation structure adj acent to the first fin-type active pattern having a relatively large width; a buried conductive structure contacting one end surface of the gate isolation structure, and connected to the second contact structure; a conductive through-structure extending from a lower surface of the substrate, and connected to the buried conductive structure; and a first wiring layer electrically connected to the first contact structure and the buried conductive structure.

公开(公告)号：EP4386828A2

公开(公告)日：2024-06-19

申请号：EP23214666.2

申请日：2023-12-06

申请人： Samsung Electronics Co., Ltd.

发明人： LEE, Kyoungwoo ,  LEE, Anthony Dongick ,  KIM, Kyungmin ,  KIM, Gukhee ,  KIM, Beomjin ,  KIM, Youngwoo ,  NA, Sangcheol ,  CHAE, Myeonggyoon ,  HA, Seungseok

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/58 ,  H01L23/60

CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L23/481 ,  H01L23/5286 ,  H01L23/60

摘要： A semiconductor device includes a semiconductor substrate having a first surface and a second surface facing away from the first surface and including, in a plan view, a main chip region and a sealing region surrounding the main chip region, a front wiring layer on the first surface of the semiconductor substrate and including a front wiring structure, a back wiring layer on the second surface of the semiconductor substrate and including a power wiring structure, a front ring structure in the front wiring layer of the sealing region, and a back ring structure in the back wiring layer of the sealing region.

公开(公告)号：EP4386828A3

公开(公告)日：2024-09-04

申请号：EP23214666.2

申请日：2023-12-06

申请人： Samsung Electronics Co., Ltd.

发明人： LEE, Kyoungwoo ,  LEE, Anthony Dongick ,  KIM, Kyungmin ,  KIM, Gukhee ,  KIM, Beomjin ,  KIM, Youngwoo ,  NA, Sangcheol ,  CHAE, Myeonggyoon ,  HA, Seungseok

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/58 ,  H01L23/60

CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L23/481 ,  H01L23/5286 ,  H01L23/60

摘要： A semiconductor device includes a semiconductor substrate having a first surface and a second surface facing away from the first surface and including, in a plan view, a main chip region and a sealing region surrounding the main chip region, a front wiring layer on the first surface of the semiconductor substrate and including a front wiring structure, a back wiring layer on the second surface of the semiconductor substrate and including a power wiring structure, a front ring structure in the front wiring layer of the sealing region, and a back ring structure in the back wiring layer of the sealing region.

公开(公告)号：EP4333070A1

公开(公告)日：2024-03-06

申请号：EP23168561.1

申请日：2023-04-18

申请人： Samsung Electronics Co., Ltd.

发明人： CHA, Seungmin ,  SONG, Seungmin ,  KIM, Youngwoo ,  KIM, Jinkyu ,  YOU, Sora ,  LEE, Namhyun ,  LEE, Sungmoon

IPC分类号： H01L29/06 ,  H01L23/528 ,  H01L29/423 ,  H01L21/336 ,  H01L29/775 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  B82Y10/00

摘要： An integrated circuit device includes a substrate, having a front surface and a rear surface opposite to each other, and a fin-type active region defined by a trench in the front surface, a device separation layer filling the trench, a source/drain region on the fin-type active region, a first conductive plug arranged on the source/drain region and electrically connected to the source/drain region, a power wiring line at least partially arranged on a lower surface of the substrate, a buried rail connected to the power wiring line through the device separation layer and decreasing in horizontal width toward the power wiring line, and a power via connecting the buried rail to the first conductive plug.