公开(公告)号：EP3963631B1

公开(公告)日：2024-09-18

申请号：EP20936072.6

申请日：2020-05-29

IPC分类号： H10B43/27 ,  H10B43/40 ,  H01L25/00 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L23/58

CPC分类号： H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/0654820130101 ,  H01L2225/0656220130101 ,  H01L23/58 ,  H01L2224/0814520130101 ,  H01L24/73 ,  H01L24/08 ,  H01L2224/0502520130101 ,  H01L2224/0554720130101 ,  H01L2224/060320130101 ,  H01L2224/8035720130101 ,  H01L2224/0918120130101 ,  H01L2224/920220130101 ,  H10B43/50 ,  H10B43/40 ,  H10B43/27

公开(公告)号：EP3264460B1

公开(公告)日：2024-08-28

申请号：EP17150830.2

申请日：2017-01-10

IPC分类号： H01L23/58 ,  G06F21/87 ,  G06K19/073 ,  G06F21/75

CPC分类号： G06F21/87 ,  G06K19/07327 ,  G06K19/07363 ,  H01L23/5227 ,  G06F21/75 ,  H01L23/576

公开(公告)号：EP4386828A2

公开(公告)日：2024-06-19

申请号：EP23214666.2

申请日：2023-12-06

申请人： Samsung Electronics Co., Ltd.

发明人： LEE, Kyoungwoo ,  LEE, Anthony Dongick ,  KIM, Kyungmin ,  KIM, Gukhee ,  KIM, Beomjin ,  KIM, Youngwoo ,  NA, Sangcheol ,  CHAE, Myeonggyoon ,  HA, Seungseok

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/58 ,  H01L23/60

CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L23/481 ,  H01L23/5286 ,  H01L23/60

摘要： A semiconductor device includes a semiconductor substrate having a first surface and a second surface facing away from the first surface and including, in a plan view, a main chip region and a sealing region surrounding the main chip region, a front wiring layer on the first surface of the semiconductor substrate and including a front wiring structure, a back wiring layer on the second surface of the semiconductor substrate and including a power wiring structure, a front ring structure in the front wiring layer of the sealing region, and a back ring structure in the back wiring layer of the sealing region.

公开(公告)号：EP4354493A1

公开(公告)日：2024-04-17

申请号：EP23191624.8

申请日：2023-08-16

申请人： Samsung Electronics Co., Ltd.

发明人： CHOO, Gyosoo ,  BYEON, Daeseok ,  YANG, Woosung

IPC分类号： H01L21/66 ,  G01R31/28 ,  H01L23/58 ,  H01L23/00

CPC分类号： H01L22/32 ,  H01L24/48 ,  H01L23/585 ,  G01R31/2884 ,  H01L21/78 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/80 ,  H01L2224/8089520130101 ,  H01L2224/8089620130101

摘要： A semiconductor device with a structure in which a plurality of chips (CP1, CP2) are stacked includes: a chip area (CA); a scribe lane (SL) at a circumference of the chip area (CA); a dam structure that separates the chip area (CA) and the scribe lane (SL); a detection wire that extends from the chip area (CA) to the scribe lane (SL) by passing through the dam structure; and a detection circuit in the chip area (CA) that is electrically connected to the detection wire and is configured to detect a defect in the scribe lane (SL).

公开(公告)号：EP4199046A3

公开(公告)日：2023-11-15

申请号：EP22204881.1

申请日：2022-11-01

申请人： INTEL Corporation

发明人： Kabir, Mohammad Enamul ,  Puls, Conor P. ,  Rahman, Tofizur ,  Zawadzki, Keith ,  Greve, Hannes

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/58 ,  H01L23/522 ,  H01L21/768 ,  H01L23/48

摘要： Embodiments described herein may be related to apparatuses, processes, and techniques for providing a hermetic seal for a layer of transistors with metal on both sides that are on a substrate. The layer of transistors may be within a die or within a portion of a die. The hermetic seal may include a hermetic layer on one side of the layer of transistors and a hermetic layer on the opposite side of the transistors. In embodiments, one or more metal walls may be constructed through the transistor layer, with metal rings placed around either side of the layer of transistors and hermetically coupling with the two hermetic layers. Other embodiments may be described and/or claimed.

公开(公告)号：EP4246569A1

公开(公告)日：2023-09-20

申请号：EP23162254.9

申请日：2023-03-16

申请人： Huawei Digital Power Technologies Co., Ltd.

发明人： TANG, Longgu ,  HU, Fei ,  GAO, Bo ,  LIU, Chia Fu ,  HUANG, Boning ,  LIU, Zhihua

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L29/06 ,  H01L23/58

摘要： A chip and an electronic device are disclosed, and relate to the field of chip technologies, to reduce a cracking risk of a passivation layer, and improve reliability of the chip. The chip is divided into a main functional area, a transition area, and a protection area, where the transition area is located between the main functional area and the protection area. The chip includes a field oxide, a metal layer, and a passivation layer that are sequentially stacked on a semiconductor substrate. The field oxide and the passivation layer are located in the transition area and the protection area, and the metal layer is located in the main functional area and the transition area. In the transition area, the field oxide includes a primary field oxide and at least one secondary field oxide that are disposed at intervals, and the secondary field oxide is located on a side of the primary field oxide facing the main functional area. In the transition area, the metal layer extends from the main functional area to a side of the primary field oxide facing away from the semiconductor substrate. The passivation layer extends from a side of the metal layer facing away from the semiconductor substrate to a side of the metal layer facing away from the main functional area to cover a surface of the side of the metal layer facing away from the semiconductor substrate and a surface of the side of the metal layer facing away from the main functional area.

公开(公告)号：EP4195254A1

公开(公告)日：2023-06-14

申请号：EP21213708.7

申请日：2021-12-10

申请人： Infineon Technologies AG

发明人： NOLTEN, Ulrich ,  WOLFF, Karsten

IPC分类号： H01L23/02 ,  H01L25/07 ,  H01L25/18 ,  H01L23/58 ,  H01L23/48

摘要： A housing (7) for a power semiconductor module arrangement (100) comprises sidewalls and a top, wherein the top comprises a first surface (701) extending in a first horizontal plane (l1) and a second surface (702) opposite and in parallel to the first surface (701), a plurality of openings of a first kind (722a), each of the plurality of openings of the first kind (722a) comprising a first through hole (722) extending through the top from the first surface (701) to the second surface (702), and a plurality of openings of a second kind (722b), each of the plurality of openings of the second kind (722b) comprising a second through hole (722) extending through the top from the first surface (701) to the second surface (702). The plurality of openings of the first kind (722a) and the plurality of openings of the second kind (722b) are arranged alternatingly in a regular pattern, each of the plurality of openings of the first kind (722a) comprises a collar or sleeve (724) arranged adjacent to and forming a closed loop around the respective first through hole (722), and each of the plurality of openings of the second kind (722b) comprises a trench or indentation (726) arranged adjacent to and forming a closed loop around the respective second through hole (722).

公开(公告)号：EP4136672A1

公开(公告)日：2023-02-22

申请号：EP21723559.7

申请日：2021-04-14

申请人： QUALCOMM Incorporated

发明人： PAUL, Abhijeet ,  MATLOUBIAN, Mishel

IPC分类号： H01L23/00 ,  H01L23/552 ,  H01L23/58 ,  H01L23/31 ,  H01L21/56 ,  H01L23/522 ,  H01L23/66

公开(公告)号：EP4115443A2

公开(公告)日：2023-01-11

申请号：EP21731049.9

申请日：2021-05-19

申请人： Siemens Aktiengesellschaft

发明人： MÜLLER, Bernd ,  NACHTIGALL-SCHELLENBERG, Christian ,  STROGIES, Jörg ,  WILKE, Klaus

IPC分类号： H01L21/56 ,  H01L21/603 ,  H01L23/58 ,  H01L23/29

公开(公告)号：EP3889683B1

公开(公告)日：2022-12-28

申请号：EP21165587.3

申请日：2021-03-29

发明人： TEYSSEDRE, Hubert ,  LANDIS, Stefan ,  MAY, Michaël

IPC分类号： H04L9/32 ,  G03F7/00 ,  G06F21/73 ,  H01L21/027 ,  H01L21/768 ,  H01L23/544 ,  H01L23/58 ,  H01L23/528 ,  B82Y40/00