公开(公告)号：EP4380332A1

公开(公告)日：2024-06-05

申请号：EP23206796.7

申请日：2023-10-30

申请人： Samsung Electronics Co., Ltd.

发明人： KIM, Jun Hyoung ,  KIM, Ji Won ,  LEE, Ah Reum ,  SUNG, Suk Kang

IPC分类号： H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50 ,  H01L23/00 ,  H01L25/18

CPC分类号： H10B43/27 ,  H10B43/40 ,  H10B43/50 ,  H10B43/10 ,  H01L24/08 ,  H01L25/18

摘要： A semiconductor memory device includes a cell substrate (100) including a first surface (100a) and a second surface (100b) opposite to the first surface, a first mold stack, MS1, including a plurality of first gate electrodes, GSL, WL11-WL1n, sequentially stacked on the first surface (100a), a second mold stack, MS2, including a plurality of second gate electrodes, WL21-WL2n, SSL, sequentially stacked on the first mold stack, MS1, a first channel structure, CH1, extending in a first direction with respect to the first surface (100a) and crossing the plurality of first gate electrodes, GSL, WL11-WL1n, and the plurality of second gate electrodes, WL21-WL2n, SSL, and an input/output pad (380) on the second surface (100b), wherein the first mold stack, MS1, includes a mold opening, MSo, that exposes a portion of the second mold stack, MS2, and at least a portion of the input/output pad (380) overlaps the mold opening in the first direction.

公开(公告)号：EP4395493A1

公开(公告)日：2024-07-03

申请号：EP23196723.3

申请日：2023-09-12

申请人： Samsung Electronics Co., Ltd.

发明人： LEE, Gil Sung ,  SUNG, Suk Kang

IPC分类号： H10B43/10 ,  H10B43/27 ,  H10B43/50 ,  H10B43/35

CPC分类号： H10B43/10 ,  H10B43/27 ,  H10B43/50 ,  H10B43/35

摘要： A semiconductor memory device may include a cell substrate, a mold structure including gate electrodes stacked on the cell substrate, a channel structures (CH1, CH2, CH3) penetrating the mold structure; and a first cutting structure (SLC) cutting some of the gate electrodes. The first cutting structure may include a first portion (SLC1) having a line shape extending in a first direction and a second portion (SLC2) having a line shape extending in a second direction. The first portion and the second portion may be alternately connected to form a zigzag shape. The first cutting structure may include a first side wall and a second side wall opposing the first side wall. A first point of the first side wall connected from the second portion to the first portion and a second point of the second side wall connected from the first portion to the second portion may be in corresponding channel structures among the channel structures.

公开(公告)号：EP4294147A1

公开(公告)日：2023-12-20

申请号：EP23164757.9

申请日：2023-03-28

申请人： Samsung Electronics Co., Ltd.

发明人： KIM, Ji Young ,  KIM, Do Hyung ,  KIM, Ji Won ,  SUNG, Suk Kang

IPC分类号： H10B41/27 ,  H10B43/27

摘要： According to some implementations of the present disclosure, a semiconductor memory device includes a semiconductor layer including a first face and a second face opposite to the first face in a first direction directed upward from the first face to the second face; a source structure including: a plate disposed on the second face of the semiconductor layer; and a plug extending from the plate through the semiconductor layer; a plurality of gate electrodes disposed on the first face of the semiconductor layer and sequentially stacked on one an other; and a channel structure that extends through the plurality of gate electrodes and that is disposed on the plug, wherein the channel structure is electrically connected to the source structure.