公开(公告)号：EP0974913B1

公开(公告)日：2009-11-25

申请号：EP98959154.0

申请日：1998-12-10

申请人： Seiko Epson Corporation

发明人： AMANO, Kazuhiko ,  NAKAMURA, Tsugio ,  KASAHARA, Hiroshi ,  SHIMODA, Tatsuya

IPC分类号： G06F17/10 ,  G06F7/22 ,  G09C1/00 ,  G06F7/72

CPC分类号： G06F7/57 ,  G06F7/535 ,  G06F7/723 ,  G06F21/72 ,  G06F2207/3816 ,  G06F2207/5353 ,  G06F2221/2149

公开(公告)号：EP0974913A1

公开(公告)日：2000-01-26

申请号：EP98959154.0

申请日：1998-12-10

申请人： Seiko Epson Corporation

发明人： AMANO, Kazuhiko ,  NAKAMURA, Tsugio ,  KASAHARA, Hiroshi ,  SHIMODA, Tatsuya

IPC分类号： G06F17/10 ,  G06F7/22 ,  G09C1/00

CPC分类号： G06F7/57 ,  G06F7/535 ,  G06F7/723 ,  G06F21/72 ,  G06F2207/3816 ,  G06F2207/5353 ,  G06F2221/2149

摘要： An information processing system that is configured in such a manner that computational processing is performed on input data in accordance with a processing sequence, for outputting data, comprises: a plurality of arithmetic units (7-1 to 7-x), each computing at an arithmetic precision 2 m bits (where m is a natural number) based on the processing sequence; and a plurality of cascade connection terminals for cascading these arithmetic units each other. When the maximum arithmetic precision that is required during computational processing is 2 n bits (where n is a natural number and is fixed), x numbers of (where x is a natural number) the arithmetic units are cascaded in a manner such that the inequality x ≥ 2 n /2 m is satisfied. When an arithmetic precision of 2 n1 bits (where n1 ≤ n, and n1 is variable) is necessary during computational processing, x1 numbers of the arithmetic units are cascaded in a manner such that the inequality x1 ≥ 2 n1 /2 m (where x1 is a natural number and is variable) is satisfied. This makes it possible to easily implement an information processing system for performing computations to any desired precision in a hardware manner, and also makes it possible to support a simple hardware-based method of expanding the arithmetic precision.

摘要翻译： 1。一种信息处理系统，其特征在于，按照处理顺序对输入数据进行计算处理并输出数据，其特征在于，具备：多个运算部（7-1〜7-x），分别计算 基于处理序列的算术精度2m比特（其中m是自然数）; 以及用于将这些运算单元彼此级联的多个级联连接端子。 当在计算处理期间所需的最大计算精度是2n位（其中n是自然数并且是固定的）时，x个（其中x是自然数）算术单元以这样的方式级联，即不等式x 满足≥2n/ 2m。 当在计算处理期间需要2n1位（其中n1≤n且n1是可变的）的算术精度时，将x1个算术单元级联以使得不等式x1≥2n1/ 2m（其中x1是自然的 数量并且是可变的）得到满足。 这使得可以容易地实现用于以硬件方式以任何期望的精度执行计算的信息处理系统，并且还使得可以支持扩展计算精度的简单的基于硬件的方法。