公开(公告)号：EP3236373A1

公开(公告)日：2017-10-25

申请号：EP17166522.7

申请日：2017-04-13

申请人： Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

发明人： HONG, Lin ,  LI, Xue

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/504 ,  G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： A method for optimizing manufacturability of standard cells includes generating random contexts for the standard cells, inserting vias into the standard cells, and performing a lithography verification on the standard cells after the vias have been inserted. The method enables early detection and resolution of potential hot spots on standard cell pin connections and reduction of hot spots that are introduced by the router at the chip level. The early detection and reduction of hot spots shortens the cycle time of a standard-cell based design.

摘要翻译： 用于优化标准单元的可制造性的方法包括为标准单元产生随机上下文，将过孔插入标准单元中，并且在已经插入过孔之后对标准单元执行光刻验证。 该方法使得能够及早检测和解决标准单元引脚连接上的潜在热点并且减少路由器在芯片级引入的热点。 热点的早期检测和减少缩短了基于标准单元的设计的周期时间。