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公开(公告)号：EP3477863A1
公开(公告)日：2019-05-01
申请号：EP17905899.5
申请日：2017-08-30
发明人： FAN, Shuo
IPC分类号： H03K17/687
摘要： A dynamic amplification circuit capable of providing a stable gain includes a first drive circuit (310) for generating a first driving voltage according to a first control signal and a first driving current; a second drive circuit (320), configured to generate a first driving signal according to the first driving voltage and a second driving voltage; a third drive circuit (330), configured to generate a second control signal according to the first control signal and the first driving signal; and a dynamic amplifier DA (340) including a first branch (101) and a second branch (102), where the first branch (101) includes a first capacitor (120), the second branch (102) includes a second capacitor, and the first branch (101) and the second branch (102) are connected by a first resistor (150) and a second resistor (160), and the dynamic amplifier DA (340) is configured to control an operation state of the dynamic amplifier DA (340) through the first control signal and the second control signal, where a duration of the dynamic amplifier DA (340) in an amplification phase is proportional to a product of a resistance value of the first resistor (150) and a capacitance value of the first capacitor (120).
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2.发明公开
公开(公告)号：EP3800790A1
公开(公告)日：2021-04-07
申请号：EP19917555.5
申请日：2019-04-03
发明人： FAN, Shuo
IPC分类号： H03M1/38
摘要： The present application provides a capacitive analog-to-digital converter, an analog-to-digital conversion system, a chip, and a device. The capacitive analog-to-digital converter includes: a first capacitor array, including N first capacitor banks that include M first capacitors, where M is a positive integer greater than N; M first switches, respectively connected to first electrode plates of the M first capacitors in a one-to-one correspondence to enable a successive approximation logic controller to control connections of the first electrode plates of the M first capacitors with an output of a voltage generation circuit and with a first sampling voltage output by controlling the M first switches; a comparator, including a first input, a second input and an output; and the successive approximation logic controller, connected to the output of the comparator, and configured to control the M first switches according to comparison results output by the output of the comparator. Not only analog-to-digital conversion is achieved, but also accuracy of the analog-to-digital conversion is improved.
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公开(公告)号：EP3343335A1
公开(公告)日：2018-07-04
申请号：EP16911786.8
申请日：2016-10-26
发明人： FAN, Shuo
IPC分类号： G06F3/044
CPC分类号： G06F3/044 , G06F3/0412 , G06F3/0418 , G06K9/0002 , G06K9/00087
摘要： Embodiments of the present invention pertain to the technical field of touch detection, and relate to a capacitance variation detection circuit, a touch screen and a touch detection method. The method includes: connecting one terminal of a detection capacitor and one terminal of a denoising capacitor to a first power simultaneously, and connecting the other terminal of the detection capacitor and the other terminal of a denoising capacitor to a reference ground simultaneously; disconnecting the detection capacitor from the first power source, and connecting the detection capacitor to the negative input terminal of the operation amplifier, switching the one terminal of the denosing capacitor from being connected to the first power source at the first stage to being connected to the reference ground, and connecting the other terminal of the denoising capacitor to the negative input terminal of the operational amplifier; and acquiring an output result of the operational amplifier, and judging whether there is a touch operation according to the output result. With the detection circuit and method according to the embodiments of the present invention, impacts caused by noise of a driving voltage and other interference signals superimposed on the driving voltage onto an output of an integrating circuit may be reduced or eliminated, and thus a signal-to-noise ratio of useful signals is improved.
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5.发明公开
公开(公告)号：EP3340472A1
公开(公告)日：2018-06-27
申请号：EP16898149.6
申请日：2016-10-25
发明人： FAN, Shuo
IPC分类号： H03M1/38
摘要： Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular, relate to a DAC capacitor array, an analog-to-digital converter, and a method for reducing power consumption of an analog-to-digital converter. The DAC capacitor array includes a plurality of sub-capacitor arrays that are connected in parallel. Each sub-capacitor array includes: a capacitor group, including N capacitors connected in parallel, N being a positive integer; and a primary switch and a plurality of multiplexers; wherein one terminal of each capacitor in the capacitor group is connected to an input terminal of a comparator, and is connected to an input source via the primary switch; and the other terminals of the capacitors in the capacitor group are connected to a plurality of input sources via corresponding multiplexers respectively. The DAC capacitor array is optimized by adjusting the reference voltage to which the capacitors in the DAC capacitor array are connected, which reduces the overall capacitance of the DAC capacitor array. In this way, the size of the SAR analog-to-digital converter is reduced, the power consumption is reduced, and meanwhile the cost of chips may be lowered in manufacture of the chips.
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公开(公告)号：EP3798645A1
公开(公告)日：2021-03-31
申请号：EP19918497.9
申请日：2019-08-01
发明人： FAN, Shuo
摘要： Provided is a capacitance detection circuit (100), which has better detection performance. The capacitance detection circuit (100) includes: a first charging and discharging circuit (110) configured to perform charging or discharging on a capacitor to be detected (111); a second charging and discharging circuit (120) configured to perform charging or discharging on a calibration capacitor (121); an analog-to-digital conversion circuit (130) configured to continuously sample a voltage difference between the capacitor to be detected (111) and the calibration capacitor (121) in a charging or discharging process to obtain sampled data; and a digital processing circuit (140) configured to detect a capacitance of the capacitor to be detected (111) according to the sampled data.
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8.发明授权
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公开(公告)号：EP3461003A1
公开(公告)日：2019-03-27
申请号：EP17896327.8
申请日：2017-07-26
发明人： FAN, Shuo
IPC分类号： H03F3/00
摘要： The present application discloses a dynamic amplification circuit, including: a first drive circuit, configured to receive a first control signal, and generate a first voltage signal and a second voltage signal; a second drive circuit, configured to receive the first voltage signal and the second voltage signal, and generate a first drive signal; a third drive circuit, configured to receive the first control signal and the first drive signal, and generate a second control signal; and a dynamic amplifier DA, configured to control turnon and turnoff of a first control switch and a second control switch respectively according to the first control signal and the second control signal, where in a first time period, the first control signal is at high level, and the second drive is at low level; in a second time period, the first control signal is at low level, and the second control signal is at high level; and in a third time period, the first control signal is at low level, and the second control signal is at low level, where duration of the second time period is inversely proportional to a transconductance of a transistor in a saturation region.
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10.发明公开DAC CAPACITOR ARRAY, SAR ANALOG-TO-DIGITAL CONVERTER AND METHOD FOR REDUCING POWER CONSUMPTION 审中-公开DAC电容阵列，SAR模拟数字转换器和降低功耗的方法
公开(公告)号：EP3322096A1
公开(公告)日：2018-05-16
申请号：EP17800998.1
申请日：2017-09-23
发明人： FAN, Shuo
IPC分类号： H03M1/18
摘要： The present invention relates to the field of integrated circuits, and relate to a DAC capacitor array, an SAR analog-to-digital converter and a method for reducing power consumption thereof. The method includes: connecting one terminal of each capacitor in a first capacitor array and a second capacitor array to a first reference voltage via a corresponding primary switch, and connecting the other terminal of each capacitor in the first capacitor array and the second capacitor array to a positive-terminal analog input signal and a negative-terminal analog input signal respectively via a corresponding multiplexer to complete sampling; determining a value of a most-significant bit by comparing an output voltage of the first capacitor array with an output voltage of the second capacitor array, maintaining or adjusting a reference voltage connected to the other terminal of each capacitor in the first capacitor array and the second capacitor array according to the value of the most-significant bit, and determining values of a second-most-significant bit and a least-significant bit by further comparing the output voltage of the first capacitor array with the output voltage of the second capacitor array. According to the embodiments of the present invention, conversion power consumption may be reduced.
摘要翻译： 集成电路领域本发明涉及集成电路领域，并且涉及DAC电容器阵列，SAR模数转换器以及用于降低其功耗的方法。 该方法包括：经由对应的初级开关将第一电容器阵列和第二电容器阵列中的每个电容器的一个端子连接到第一参考电压，并且将第一电容器阵列和第二电容器阵列中的每个电容器的另一个端子连接到 正端模拟输入信号和负端模拟输入信号分别经相应的多路复用器完成采样; 通过比较第一电容器阵列的输出电压和第二电容器阵列的输出电压来确定最高有效位的值，维持或调整连接到第一电容器阵列中的每个电容器的另一端子的参考电压， 根据最高有效位的值确定第二电容器阵列，并且通过进一步比较第一电容器阵列的输出电压与第二电容器的输出电压来确定第二最高有效位和最低有效位的值 阵列。 根据本发明的实施例，可以减少转换功耗。
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