公开(公告)号：EP1411431A3

公开(公告)日：2010-10-20

申请号：EP03020154.5

申请日：2003-09-05

申请人： Sicronic Remote KG, LLC

发明人： Goel, Ashish Kumar ,  Khanna, Namerita ,  Aggarwal, Davinder

IPC分类号： G06F11/14 ,  G06F17/50

CPC分类号： G06F11/1402 ,  G01R31/318519 ,  G06F11/1008

摘要： The invention provides an improved method and apparatus for reloading only those frames in which errors are detected during the FPGA configuration. A configuration data frame for a FPGA is sumultaneously loaded to the Frame register of the FPGA and also to an error detection circuit which detects errors with the loaded frame. An error counter value is maintained by the apparatus and is incremented each time an error with a frame is detected. The incremented value is compared by a Comparator circuit with a pre-determined threshold value 'n'. If a match is found then the configuration process is aborted, else the data frame is reloaded in the configuration memory, transferred again to the frame register and recheked for errors. If no error os detected with the reloaded frame, the error counter value is reset and the next frame is loaded until the FPGA configuration process is over.