公开(公告)号：EP1334594A2

公开(公告)日：2003-08-13

申请号：EP01989823.8

申请日：2001-10-30

申请人： Silicon Image, Inc.

发明人： KIM, Gyudong ,  KIM, Min-Kyu ,  HWANG, Seung, Ho

IPC分类号： H04L25/49

CPC分类号： H04L25/0292 ,  H04L1/12 ,  H04L7/0008 ,  H04L25/0272 ,  H04L25/028

摘要： The system preferably includes a unique transmitter that sends both clock and data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge (T0, T1, T3, T4) for pulse with modulation by the data (00, 01, 10, 11). The falling edge position is decoded by the receiver to extract data from the clock signal. The receiver comprises a clock re-generator, a data decoder and a returm channel encoder. The clock re-generator monitors the transmission line, receives signals, filters them and generates a clock signal at the receiver from the signal on the transmission line. The return channel encoder generates signals and asserts them on the transmission line. The signal is asserted or superimposed over the clock & data signal provided by the transmitter.

公开(公告)号：EP2673685A2

公开(公告)日：2013-12-18

申请号：EP12744257.2

申请日：2012-02-06

申请人： Silicon Image, Inc.

发明人： KIM, Gyudong ,  KIM, Eungu ,  KIM, Min-Kyu ,  SHIM, Daeyun ,  SHARMA, Ravi ,  KIM, Myounghwan ,  LEE, Jaeryon

IPC分类号： G06F1/32 ,  G06F13/14

CPC分类号： G06F1/3287 ,  G06F1/3246 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D50/20

摘要： Embodiments of the invention are generally directed to a low power standby mode control circuit. An embodiment of an apparatus includes a processor, an interface for a connection with a second apparatus, and an operational circuit, wherein the processor is to disable one or more power connections to the operational circuit in a standby mode. The apparatus further includes a standby mode control circuit, the standby control circuit to operate using a standby power source, wherein the standby mode control circuit is to detect a stimulus signal from the second apparatus and in response to the stimulus signal the standby control circuit is to signal the processor, the processor to enable the one or more power connections of the operational circuit.

公开(公告)号：EP2947809A1

公开(公告)日：2015-11-25

申请号：EP15177026.0

申请日：2007-10-31

申请人： Silicon Image, Inc.

发明人： SHIM, Daeyun ,  KIM, Min-Kyu ,  KIM, Gyudong ,  JUNG, Keewook ,  HWANG, Seung Ho

IPC分类号： H04L5/20

CPC分类号： H04L5/20

摘要： The present disclosure relates to a chip comprising transmitters configured to transmit differential signals on conductors, wherein the conductors include first and second pairs of conductors, and the differential signals include first differential signals to be transmitted to the first pair of conductors and second differential signals to be transmitted to the second pair of conductors. The chip furhter comprises a current mode circuitry configured to selectively modulate a common mode voltage of the differential signals to communicate data and and a common mode detection circuitry configured to detect changes in the common mode voltage. Furthermore, the present disclosure relates to a second chip including receivers configured to receive differential signals on conductors, wherein the conductors include first and second pairs of conductors, and the differential signals include first differential signals to be received by the first pair of conductors and second differential signals to be received by the second pair of conductors. The second chip further comprises a current mode circuitry configured to selectively modulate a common mode voltage of the differential signals to communicate data and a common mode detection circuitry configured to detect changes in the common mode voltage.

摘要翻译： 本公开涉及一种包括发射机的芯片，该发射机被配置为在导体上传输差分信号，其中导体包括第一和第二对导体，并且差分信号包括要传输到第一对导体的第一差分信号和第二差分信号， 被传输到第二对导体。 芯片形成器包括被配置为选择性地调制差分信号的共模电压以传送数据的电流模式电路，以及被配置为检测共模电压的变化的共模检测电路。 此外，本公开涉及包括被配置为在导体上接收差分信号的接收器的第二芯片，其中所述导体包括第一和第二对导体，并且所述差分信号包括要由第一对导体接收的第一差分信号和第二对导体 差分信号由第二对导体接收。 第二芯片还包括被配置为选择性地调制差分信号的共模电压以传送数据的电流模式电路，以及被配置为检测共模电压的变化的共模检测电路。

公开(公告)号：EP1112648A1

公开(公告)日：2001-07-04

申请号：EP99946778.0

申请日：1999-09-10

申请人： Silicon Image, Inc.

发明人： KIM, Gyudong ,  KIM, Min-Kyu ,  HWANG, Seung, Ho

IPC分类号： H04L25/02 ,  H04L25/49

CPC分类号： G09G5/006 ,  G09G5/008 ,  G09G2370/04 ,  H04L7/0008 ,  H04L25/4902

摘要： The system preferably includes a unique transmitter that sends both clock and data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge. The falling edge position is decoded by the receiver to extract data from the clock signal. The receiver comprises a clock re-generator, a data decoder and a return channel encoder. The clock re-generator monitors the transmission line, receives signals, filters them and generates a clock signal at the receiver from the signal on the transmission line. The return channel encoder generates signals and asserts them on the transmission line. The signal is asserted or superimposed over the clock and data signal provided by the transmitter.

公开(公告)号：EP3306851A1

公开(公告)日：2018-04-11

申请号：EP17200793.2

申请日：2007-10-31

申请人： Silicon Image, Inc.

发明人： SHIM, Daeyun ,  KIM, Min-Kyu ,  KIM, Gyudong ,  JUNG, Keewook ,  HWANG, Seung Ho

IPC分类号： H04L5/20

CPC分类号： H04L5/20

摘要： A system comprising a transmitter chip and a receiver chip is disclosed. The transmitter chip comprises a first transmitter circuit configured to transmit a first differential signal on a first pair of conductors and common mode detection circuitry configured to detect changes in a first common mode voltage of the first pair of conductors to obtain a first common mode data signal. The receiver chip comprises a first receiver circuit configured to receive the first differential signal from the first pair of conductors and current mode circuitry configured to modulate the first common mode voltage of the first pair of conductors to communicate the first common mode data signal to the transmitter chip.

摘要翻译： 公开了一种包括发射器芯片和接收器芯片的系统。 发送器芯片包括被配置为在第一对导体上发送第一差分信号的第一发送器电路以及被配置为检测第一对导体的第一共模电压的变化以获得第一共模数据信号的共模检测电路 。 接收器芯片包括被配置为从第一对导体接收第一差分信号的第一接收器电路以及被配置为调制第一对导体的第一共模电压以将第一共模数据信号传送到发射器的电流模式电路 芯片。

公开(公告)号：EP1112648B1

公开(公告)日：2004-12-29

申请号：EP99946778.0

申请日：1999-09-10

申请人： Silicon Image, Inc.

发明人： KIM, Gyudong ,  KIM, Min-Kyu ,  HWANG, Seung, Ho

IPC分类号： H04L25/02 ,  H04L25/49

CPC分类号： G09G5/006 ,  G09G5/008 ,  G09G2370/04 ,  H04L7/0008 ,  H04L25/4902

摘要： The system preferably includes a unique transmitter that sends both clock and data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge. The falling edge position is decoded by the receiver to extract data from the clock signal. The receiver comprises a clock re-generator, a data decoder and a return channel encoder. The clock re-generator monitors the transmission line, receives signals, filters them and generates a clock signal at the receiver from the signal on the transmission line. The return channel encoder generates signals and asserts them on the transmission line. The signal is asserted or superimposed over the clock and data signal provided by the transmitter.

公开(公告)号：EP1396131A2

公开(公告)日：2004-03-10

申请号：EP02739876.7

申请日：2002-06-14

申请人： Silicon Image, Inc.

发明人： KIM, Gyudong ,  KIM, Min-Kyu

IPC分类号： H04L27/04 ,  H04L27/12 ,  H04L27/20 ,  H04L27/06 ,  H04L27/14 ,  H04L27/22

CPC分类号： H04N7/083 ,  H04B1/406 ,  H04L25/45

摘要： The present invention relates to a serial interface transmission system with more than one data line, in which the transmitted data has in-band and out-of-band characters. More particularly, the present invention relates to methods and systems for sending side channel data over a high-speed digital communications link. One embodiment of the invention provides a high-speed digital transmitter (20) capable of sending side channel data. The transmitter (20) includes a channel zero encoder (50a), a multiplexer (90), data enable out control logic (92), and a channel one encoder (52a). Another embodiment of the invention provides a high-speed digital receiver (60) capable of receiving side channel data. The receiver (60) includes a channel zero decoder (50b), a channel one decoder (52b), DEI signal and FIFO control signal recovery logic (199), and a channel one de-multiplexer (140).