-
1.发明公开
公开(公告)号：EP1027657A1
公开(公告)日：2000-08-16
申请号：EP98936927.7
申请日：1998-07-22
申请人： Sonics, Inc.
IPC分类号： G06F13/00
CPC分类号： G06F13/37
摘要： The present invention provides for an on-chip communications method with fully distributed control combining a fully-pipelined, fixed latency, synchronous bus (35) with a two-level arbitration scheme where the first level of arbitration is a framed, time division multiplexing arbitration scheme and the second level is a fairly-allocated round-robin scheme implemented using a token passing mechanism. Both the latency and the bandwidth allocation are software programmable in real-time operation of the system. The present invention also provides for a communication system where access to a shared resource (10, 15, 20) is controlled by the communications protocol. Access to and from the shared resource (10, 15, 20) from the subsystem is through a bus interface module (40, 45, 50, 55, 60). The bus interface modules (40, 45, 50, 55, 60) provide a level of indirection between the subsystem (25, 30) to be connected to the shared resource (10, 15, 20). This allows the decoupling of system performance requirements. Communication over the bus (35) is fully memory mapped.
-
公开(公告)号：EP1325419A1
公开(公告)日：2003-07-09
申请号：EP01962072.3
申请日：2001-08-08
申请人： Sonics, Inc.
发明人： WINGARD, Drew, Eric , MEYER, Michael, J. , ROSSEEL, Geert, P. , ROBINSON, Lisa , TOMLINSON, Jay
IPC分类号： G06F13/00
CPC分类号： G06F17/5045 , G06F2217/66
摘要： A core block with a highly configurable interface such that the interface of the core can be optimally configured for the system the core is integrated into. In one embodiment the method consists of defining a configurable interface with different configuration options, capturing the specific core configuration through manual entry or through the use of a Graphical User Interface, and providing for software that combines the source description of the core with the configuration data to generate the core with an optimally configured logic and circuit interface.
-
公开(公告)号：EP1131729A1
公开(公告)日：2001-09-12
申请号：EP99965799.2
申请日：1999-11-12
申请人： Sonics, Inc.
IPC分类号： G06F13/00
CPC分类号： H04L12/403 , G06F13/385 , G06F13/4243 , H04L12/66
摘要： A communication system (2000) is disclosed. One embodiment includes at least two functional blocks, wherein a first functional block (1002) communicates with a second functional block (1008) by establishing a connection, wherein the connection is a logical state in which data may pass between the first functional block (1002) and the second functional block (1008). Another embodiment includes a bus coupled to each of the functional blocks and configured to carry a plurality of signals. The plurality of signals includes a connection identifier that indicates a particular connection that a data transfer is part of, and a thread identifier that indicates a transaction stream that the data transfer is part of.
-
公开(公告)号：EP1131729B1
公开(公告)日：2012-03-28
申请号：EP99965799.2
申请日：1999-11-12
申请人： Sonics, Inc.
IPC分类号： G06F13/00
CPC分类号： H04L12/403 , G06F13/385 , G06F13/4243 , H04L12/66
摘要： A communication system (2000) is disclosed. One embodiment includes at least two functional blocks, wherein a first functional block (1002) communicates with a second functional block (1008) by establishing a connection, wherein the connection is a logical state in which data may pass between the first functional block (1002) and the second functional block (1008). Another embodiment includes a bus coupled to each of the functional blocks and configured to carry a plurality of signals. The plurality of signals includes a connection identifier that indicates a particular connection that a data transfer is part of, and a thread identifier that indicates a transaction stream that the data transfer is part of.
-
5.发明授权
公开(公告)号：EP1027657B1
公开(公告)日：2005-11-16
申请号：EP98936927.7
申请日：1998-07-22
申请人： Sonics, Inc.
IPC分类号： G06F13/372
CPC分类号： G06F13/37
摘要： The present invention provides for an on-chip communications method with fully distributed control combining a fully-pipelined, fixed latency, synchronous bus (35) with a two-level arbitration scheme where the first level of arbitration is a framed, time division multiplexing arbitration scheme and the second level is a fairly-allocated round-robin scheme implemented using a token passing mechanism. Both the latency and the bandwidth allocation are software programmable in real-time operation of the system. The present invention also provides for a communication system where access to a shared resource (10, 15, 20) is controlled by the communications protocol. Access to and from the shared resource (10, 15, 20) from the subsystem is through a bus interface module (40, 45, 50, 55, 60). The bus interface modules (40, 45, 50, 55, 60) provide a level of indirection between the subsystem (25, 30) to be connected to the shared resource (10, 15, 20). This allows the decoupling of system performance requirements. Communication over the bus (35) is fully memory mapped.
-
公开(公告)号：EP1370939A1
公开(公告)日：2003-12-17
申请号：EP02709610.6
申请日：2002-02-19
申请人： Sonics, Inc.
发明人： WEBER, Wolf-Dietrich , ARAS, Richard , ROBINSON, Lisa, A. , ROSSEEL, Geert, P. , TOMLINSON, Jay, S. , WINGARD, Drew, Eric
IPC分类号： G06F9/54
摘要： A communication system (100). One embodiment includes at least two functional blocks (102, 104), wherein a first functional block (102) communicates with a second functional block (104) by establishing a connection. A connection is a logical state in which data may pass between the first functional block (102) and the second functiohnal block (104). One embodiment includes a bus (112) coupled to each of the functional blocks (102, 104) and configured to carry a plurality of signals. The plurality of signals includes a thread identifier that indicates a transaction stream the data transfer is part of and a busy signal identified by the thread identifier. The busy signal is issued by the target functional block when resources will be unavailable to perform a transfer.
-
-
-
-
-
搜索结果
6 条记录 (耗时 0.012 秒)
