公开(公告)号：EP2075918A2

公开(公告)日：2009-07-01

申请号：EP08254061.8

申请日：2008-12-18

申请人： Sony Corporation

发明人： Shinagawa, Masashi ,  Noda, Makoto ,  Yamagishi, Hiroyuki

IPC分类号： H03M13/09

CPC分类号： H03M13/00 ,  H03M13/033 ,  H03M13/09

摘要： A transmission apparatus includes: a CRC encoding processing unit configured to include a plurality of generating polynomials for an CRC encoding processing with each of a plurality of data of which the code lengths differ as a target, and employ the optimal generating polynomial out of the plurality of generating polynomials to perform the CRC encoding processing; and a transmission unit configured to transmit data obtained by the CRC encoding processing unit performing the CRC encoding processing.

摘要翻译： 发送装置包括：CRC编码处理单元，被配置为包括用于CRC编码处理的多个生成多项式，其中码长度不同的多个数据中的每一个作为目标，并且使用多个中的最优生成多项式 产生多项式以执行CRC编码处理; 以及发送单元，被配置为发送由CRC编码处理单元获得的执行CRC编码处理的数据。

公开(公告)号：EP1487028A1

公开(公告)日：2004-12-15

申请号：EP04252673.1

申请日：2004-05-07

申请人： Sony Corporation

发明人： Noda, Makoto

IPC分类号： H01L51/20 ,  H01L51/40

CPC分类号： H01L29/78696 ,  H01L51/001 ,  H01L51/0012 ,  H01L51/0052 ,  H01L51/0545

摘要： A field effect transistor comprises, at least, a channel forming region formed in a semiconductor layer, and a gate electrode provided in face-to-face relation with the channel forming region via a gate insulating film, wherein the semiconductor layer is made of a mixture of a semiconductor material layer and conductive particles. The field effect transistor is capable of enhancing a carrier mobility.

摘要翻译： 场效应晶体管至少包括形成在半导体层中的沟道形成区域和经由栅极绝缘膜与沟道形成区域面对面地设置的栅电极，其中半导体层由 半导体材料层和导电颗粒的混合物。 场效应晶体管能够增强载流子迁移率。

公开(公告)号：EP2339583A3

公开(公告)日：2014-01-22

申请号：EP10189954.0

申请日：2010-11-04

申请人： Sony Corporation

发明人： Noda, Makoto

IPC分类号： G11B20/18 ,  G11B20/14 ,  H03M13/00

CPC分类号： G11B20/1833 ,  G11B20/14 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/31 ,  H03M13/6343

摘要： Disclosed herein is a coding method including the step of: coding an information sequence in such a manner that upon performing error correction coding after carrying out RLL coding of the information sequence, the maximum number of consecutive 1-bits or 0-bits is α-β or less in an RLL code word over a range from bit p-α to bit p+α-1 of the RLL code word and that a β-bit error correcting code parity sequence is inserted between bit p-1 and bit p of the RLL code word, where α is a number larger than 1 representing the maximum number of consecutive 0-bits or 1-bits in an n-bit RLL code word and where p is a natural number.

公开(公告)号：EP1887703A1

公开(公告)日：2008-02-13

申请号：EP07018448.6

申请日：2000-09-05

申请人： Sony Corporation

发明人： Noda, Makoto

IPC分类号： H03M13/31 ,  G11B20/10 ,  H03M13/25

CPC分类号： G11B20/10212 ,  G11B20/10009 ,  G11B20/10055 ,  H03M13/256 ,  H03M13/31

摘要： Apparatus and method for decoding of a trelils code applicable to a recording/reproducing apparatus, like e.g. an AIT2 (Advanced Intelligent Tape System 2) tape streamer system. The trellis code has no DC component and no Nyquist frequency component. For encoding, a code word is generated according to a fnite state transition chart wherein the cumulative DC electric charges (RDS) and cumulative AC electric charges (ADS) of the code series are set to finite vaIues. The trellis code word, which has been NRZI-modulated, can be decoded without referring to its tail code (bit) and without referring to its head code (bit), when the above-mentioned trellis code word cannot take the start point at a plurality of states.

摘要翻译： 用于解码适用于记录/再现装置的trelils码的装置和方法，例如， AIT2（高级智能磁带系统2）磁带机系统。 网格码没有直流分量，没有奈奎斯特频率分量。 对于编码，根据虚拟状态转换图生成代码字，其中代码序列的累积DC电荷（RDS）和累积AC电荷（ADS）被设置为有限的值。 已经被NRZI调制的网格码字可以在不参考其尾码（位）的情况下进行解码，而不参考其头码（位），当上述网格码字不能在起始点处 多个州。

公开(公告)号：EP2523351A1

公开(公告)日：2012-11-14

申请号：EP12179342.6

申请日：2008-07-10

申请人： Sony Corporation

发明人： Noda, Makoto

IPC分类号： H03M13/19 ,  H03M13/15

CPC分类号： H03M13/13 ,  H03M13/033 ,  H03M13/1102 ,  H03M13/6393

摘要： The present invention relates to coding method and coding device that allow Rate-Compatible LDPC (low-density parity-check) codes to have favorable BER performance both with a low code rate and with a high code rate. In coding of LDPC codes that have plural code rates and whose all parity check matrices are composed of plural cyclic matrices, a coder 121 performs the coding in such a way that 1 0 and w 1 0 are satisfied when the maximum column weight of the cyclic matrices in the check matrix of a certain code whose code rate is not the minimum value among the LDPC codes is defined as w 0 and the maximum column weight of the cyclic matrices in the check matrix of a code having a code rate lower than that of the certain code is defined as w 1 .

摘要翻译： 本发明涉及允许速率兼容LDPC（低密度奇偶校验）码具有低码率和高码率的良好BER性能的编码方法和编码装置。 在具有多个码率并且其全部奇偶校验矩阵由多个循环矩阵组成的LDPC码的编码中，编码器121以满足1

公开(公告)号：EP2075918A3

公开(公告)日：2012-09-12

申请号：EP08254061.8

申请日：2008-12-18

申请人： Sony Corporation

发明人： Shinagawa, Masashi ,  Noda, Makoto ,  Yamagishi, Hiroyuki

IPC分类号： H03M13/09 ,  H03M13/03

CPC分类号： H03M13/00 ,  H03M13/033 ,  H03M13/09

摘要： A transmission apparatus includes: a CRC encoding processing unit configured to include a plurality of generating polynomials for an CRC encoding processing with each of a plurality of data of which the code lengths differ as a target, and employ the optimal generating polynomial out of the plurality of generating polynomials to perform the CRC encoding processing; and a transmission unit configured to transmit data obtained by the CRC encoding processing unit performing the CRC encoding processing.

公开(公告)号：EP1978644A1

公开(公告)日：2008-10-08

申请号：EP08006514.7

申请日：2008-03-31

申请人： Sony Corporation

发明人： Yamagishi, Hiroyuki ,  Noda, Makoto

IPC分类号： H03M13/11 ,  H03M13/15

CPC分类号： H03M13/116 ,  H03M13/118 ,  H03M13/15 ,  H03M13/616 ,  H03M13/6502

摘要： The application relates to the efficient encoding of quasi-cyclic codes. The parity-check matrix of a quasi-cyclic code is transformed by means of column permutations and elementary row operations into a plurality of parity-check matrices, each of which comprises two parts, wherein one part is the identity matrix. Encoding is performed by means of shift registers, which are defined by the remaining part of that transformed parity-check matrix that makes the complexity of the shift registers minimum. This could be achieved by e.g. selecting the transformed matrix having the minimum number of non-zero elements.

摘要翻译： 该应用涉及准循环码的有效编码。 准循环码的奇偶校验矩阵通过列排列和基本行操作被转换成多个奇偶校验矩阵，每个奇偶校验矩阵包括两部分，其中一部分是单位矩阵。 通过移位寄存器执行编码，移位寄存器由该变换的奇偶校验矩阵的剩余部分定义，这使得移位寄存器的复杂度最小。 这可以通过例如 选择具有最小数量的非零元素的变换矩阵。

公开(公告)号：EP1978644B1

公开(公告)日：2014-12-31

申请号：EP08006514.7

申请日：2008-03-31

申请人： Sony Corporation

发明人： Yamagishi, Hiroyuki ,  Noda, Makoto

IPC分类号： H03M13/11 ,  H03M13/15

CPC分类号： H03M13/116 ,  H03M13/118 ,  H03M13/15 ,  H03M13/616 ,  H03M13/6502

公开(公告)号：EP2339583A2

公开(公告)日：2011-06-29

申请号：EP10189954.0

申请日：2010-11-04

申请人： Sony Corporation

发明人： Noda, Makoto

IPC分类号： G11B20/18 ,  G11B20/14

CPC分类号： G11B20/1833 ,  G11B20/14 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/31 ,  H03M13/6343

摘要： Disclosed herein is a coding method including the step of: coding an information sequence in such a manner that upon performing error correction coding after carrying out RLL coding of the information sequence, the maximum number of consecutive 1-bits or 0-bits is α-β or less in an RLL code word over a range from bit p-α to bit p+α-1 of the RLL code word and that a β-bit error correcting code parity sequence is inserted between bit p-1 and bit p of the RLL code word, where α is a number larger than 1 representing the maximum number of consecutive 0-bits or 1-bits in an n-bit RLL code word and where p is a natural number.

公开(公告)号：EP1968198A1

公开(公告)日：2008-09-10

申请号：EP08003981.1

申请日：2008-03-04

申请人： Sony Corporation

发明人： Noda, Makoto

IPC分类号： H03M5/14 ,  G11B20/14

CPC分类号： G11B20/1426 ,  G11B2020/1446 ,  G11B2020/1449 ,  G11B2020/1473 ,  H03M5/145

摘要： Methods and apparatuses for encoding and decoding RLL MTR codes such as a rate 16/17 RLL(6) MTR(4) code and a rate 24/25 RLL(6) MTR(4) code. The encoding method comprises a step of converting a data word into a temporary codeword according to a conversion table for enforcing RLL and MTR constraints, a step of checking violations of the maximum-runlength constraint when concatenating a present and an earlier codeword, and when a violation is detected, a step of selecting one of the present or earlier temporary codeword which has at least four contiguous zeroes adjacent to their boundary, and a step of converting the four zeroes in order to meet the maximum-runlength constraint. Error propagation is reduced by converting one word only upon detection of RLL violation.

摘要翻译： 用于编码和解码诸如速率16/17 RLL（6）MTR（4）码和速率24/25 RLL（6）MTR（4）码的RLL MTR码的方法和装置。 编码方法包括根据用于强制RLL和MTR约束的转换表将数据字转换成临时码字的步骤，当连接当前和较早的码字时检查违反最大游程约束的步骤，以及当一个 检测到违规;选择当前或较早期临时码字之一的步骤，该临时码字与其边界相邻具有至少四个连续零点;以及转换四个零以便满足最大游程长度约束的步骤。 通过在检测到RLL违例时仅转换一个字来减少误差传播。