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公开(公告)号：EP3119000A1
公开(公告)日：2017-01-18
申请号：EP15177206.8
申请日：2015-07-17
IPC分类号： H03L7/085
CPC分类号： H03L7/0814 , H03L7/085 , H03L7/091 , H03L7/093 , H03L2207/50
摘要： The present invention relates to an all-digital Phase-Locked Loop comprising
- a reference phase generator (PHR) arranged for receiving a digital signal and for splitting the digital signal into an integer part (PHR_I) and a fractional part (PHR_F),
- an estimator block (20) arranged for estimating a control signal,
- a digital-to-time converter (30) arranged for receiving the estimated control signal and a reference clock signal (FREF) and arranged for deriving a delayed reference clock signal () using the reference clock signal and the estimated control signal,
- a time-to-digital converter (40) arranged for receiving the delayed reference clock signal and a desired clock signal phase () and for deriving a fractional phase error,
characterised in that the estimator block is arranged for receiving the fractional phase error and for determining the estimated control signal by
* correlating the fractional phase error with a version () of said fractional part having zero mean, yielding a correlated signal (),
* multiplying the correlated signal with its absolute value,
* integrating the outcome () of said multiplying to so obtain the estimated control signal.摘要翻译： 全数字锁相环技术领域本发明涉及一种全数字锁相环，包括 - 参考相位发生器（PHR），用于接收数字信号并将数字信号分成整数部分（PHR_I）和小数部分（PHR_F） 布置成用于估计控制信号的估计器块（20）， - 布置成用于接收所估计的控制信号和参考时钟信号（FREF）的数字 - 时间转换器（30），用于导出延迟的参考时钟信号（） 使用所述参考时钟信号和所述估计的控制信号， - 时间 - 数字转换器（40），被布置用于接收延迟的参考时钟信号和期望的时钟信号相位（）并且用于导出分数相位误差，其特征在于， 估计块被布置成用于接收分数相位误差，并且通过将分数相位误差与具有零均值的所述分数部分的版本（）相关来确定估计的控制信号，产生一个 相关信号（），*将相关信号与其绝对值相乘，*积分所述乘法的结果（），从而获得估计的控制信号。
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公开(公告)号：EP3119000B1
公开(公告)日：2018-03-28
申请号：EP15177206.8
申请日：2015-07-17
IPC分类号： H03L7/085
CPC分类号： H03L7/0814 , H03L7/085 , H03L7/091 , H03L7/093 , H03L2207/50
摘要： The present invention relates to an all-digital Phase-Locked Loop comprising - a reference phase generator (PHR) arranged for receiving a digital signal and for splitting the digital signal into an integer part (PHR_I) and a fractional part (PHR_F), - an estimator block (20) arranged for estimating a control signal, - a digital-to-time converter (30) arranged for receiving the estimated control signal and a reference clock signal (FREF) and arranged for deriving a delayed reference clock signal () using the reference clock signal and the estimated control signal, - a time-to-digital converter (40) arranged for receiving the delayed reference clock signal and a desired clock signal phase () and for deriving a fractional phase error, characterised in that the estimator block is arranged for receiving the fractional phase error and for determining the estimated control signal by * correlating the fractional phase error with a version () of said fractional part having zero mean, yielding a correlated signal (), * multiplying the correlated signal with its absolute value, * integrating the outcome () of said multiplying to so obtain the estimated control signal.
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公开(公告)号：EP2905905A1
公开(公告)日：2015-08-12
申请号：EP14178858.8
申请日：2014-07-29
发明人： Liu, Yao-Hong , Dolmans, Wilhelmus Matthias Clemens , van den Heuvel, Johannes Henricus Cornelus
CPC分类号： H04L27/22 , H03J1/005 , H04B1/0028 , H04B1/30 , H04L27/148 , H04L27/152
摘要： The present disclosure relates to a front-end system for a radio device comprising a converter, the converter comprising a mixer configured for down-converting a radio frequency signal into a baseband signal by using a local oscillator signal generated by a signal generator, and characterized in that, said converter further comprises a quantizer arranged for quantizing said baseband signal into a digital signal, and wherein the signal generator is configured for generating, based on said digital signal, said local oscillator signal such that it is synchronized with the radio frequency signal.
摘要翻译： 本公开涉及一种用于无线电设备的前端系统，包括转换器，该转换器包括一个混频器，该混频器被配置为通过使用由信号发生器产生的本地振荡器信号将射频信号下变频为基带信号， 其特征在于，所述转换器还包括量化器，用于将所述基带信号量化为数字信号，并且其中所述信号发生器被配置为基于所述数字信号产生所述本地振荡器信号，使得其与射频信号同步 。
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