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    BIAS CIRCUIT AND POWER AMPLIFIER CIRCUIT
    1.
    发明公开
    BIAS CIRCUIT AND POWER AMPLIFIER CIRCUIT 审中-公开

    公开(公告)号：EP4398483A3

    公开(公告)日：2024-10-16

    申请号：EP24177413.2

    申请日：2019-08-29

    申请人： Telefonaktiebolaget LM Ericsson (publ)

    发明人： Elgaard, Christian ,  SJÖLAND, Henrik

    IPC分类号： H03F1/02 ,  H03F3/213 ,  H03F3/45 ,  H03F1/22

    摘要： A bias circuit (200) for a PA (100) is disclosed. It comprises a first transistor (M1) having its drain terminal and its gate terminal connected to a first circuit node (x) and its source terminal connected to a first supply terminal (GND), a first current source (I1) connected to the first circuit node (x), and a digitally controllable first resistor (R1) connected between the first circuit node (x) and a second circuit node (y). It further comprises a second transistor (M2) configured to receive a first component (RFinp) of a differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node (y) and its source terminal connected to a second supply terminal (VDD), and a third transistor (M3) configured to receive a second component (RFinn) of the differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node (y) and its source terminal connected to a second supply terminal (VDD). The gate terminals of the second transistor (M2) and the third transistor (M3) are configured to be biased by a digitally controllable first voltage (V1). The bias circuit is configured to generate a bias voltage (Vbias) for the PA (100) at the second circuit node (y).

    FINE FREQUENCY DIGITAL OSCILLATOR TUNING
    8.
    发明公开
    FINE FREQUENCY DIGITAL OSCILLATOR TUNING 审中-公开

    公开(公告)号：EP3826171A1

    公开(公告)日：2021-05-26

    申请号：EP20198986.0

    申请日：2016-10-07

    申请人： Telefonaktiebolaget LM Ericsson (publ)

    发明人： SJÖLAND, Henrik ,  SANDSTRÖM, Torbjörn

    IPC分类号： H03B5/12

    摘要： A switched capacitor arrangement (200) for tuning a differential circuit is disclosed. The switched capacitor arrangement (200) comprises a first node (211), a second node (212) and a third node (213). The switched capacitor arrangement (200) further comprises a first capacitor (C1) coupled between the first node (211) and the second node (212), a second capacitor (C2) coupled between the second node (212) and the third node (213), and a first switch branch comprising a first switch (S1) coupled between the second node (212) and a signal ground node. The first switch (S1) has an on state and an off state. The first node (211) and third node (213) are configured to be connected to respective differential nodes (Vtank, -Vtank) of the differential circuit. The switched capacitor arrangement (200) is configured to tune the differential circuit by controlling the state of the first switch (S1).

    PHASE LOCKED LOOP, PHASE LOCKED LOOP ARRANGEMENT, TRANSMITTER AND RECEIVER AND METHOD FOR PROVIDING AN OSCILLATOR SIGNAL
    10.
    发明公开
    PHASE LOCKED LOOP, PHASE LOCKED LOOP ARRANGEMENT, TRANSMITTER AND RECEIVER AND METHOD FOR PROVIDING AN OSCILLATOR SIGNAL 审中-公开

    公开(公告)号：EP3440775A1

    公开(公告)日：2019-02-13

    申请号：EP16714945.9

    申请日：2016-04-08

    申请人： Telefonaktiebolaget LM Ericsson (PUBL)

    发明人： SJÖLAND, Henrik ,  PÅHLSSON, Tony

    IPC分类号： H03L7/087 ,  H03L7/085

    摘要： A phase locked loop, for a particularly in a beamforming system comprises a digital loop filter to provide a digital control word to a controllable oscillator; a frequency divider configured to provide a first feedback signal and a second feedback signal in response to an oscillator signal, the second feedback signal delayed with respect to the first feedback signal; a first comparator path configured to receive the first feedback signal and a second comparator path configured to receive the second feedback signal, each of the first and second comparator path configured to provide a respective phase delay signal to the digital loop filter in response to a respective adjustment signal and a phase deviation between a common reference signal and the respective feedback signal.