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公开(公告)号:EP0840512A3
公开(公告)日:2001-01-31
申请号:EP97119123.4
申请日:1997-11-03
CPC分类号: H04N21/8166 , G09G5/14 , G09G5/395 , H04N5/44 , H04N5/4401 , H04N5/44508 , H04N11/20 , H04N19/42 , H04N19/436 , H04N19/61 , H04N21/426 , H04N21/42615 , H04N21/42623 , H04N21/42653 , H04N21/4305 , H04N21/431 , H04N21/43632 , H04N21/439 , H04N21/44 , H04N21/443
摘要: An improved audio-visual circuit is provided that includes a transport packet parsing circuit for receiving a transport data packet stream, a CPU circuit for initializing said integrated circuit and for processing portions of said data packet stream, a ROM circuit for storing data, a RAM circuit for storing data, an audio decoder circuit for decoding audio portions of said data packet stream, a video decoder circuit for decoding video portions of said data packet stream, an NTSC/PAL encoding circuit for encoding video portions of said data packet stream, an OSD coprocessor circuit for processing OSD portions of said data packets, a traffic controller circuit moving portions of said data packet stream between portions of said integrated circuit, an extension bus interface circuit, a P1394 interface circuit, a communication coprocessors circuit, an address bus connected to said circuits, and a data bus connected to said circuits.
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公开(公告)号:EP0840512A2
公开(公告)日:1998-05-06
申请号:EP97119123.4
申请日:1997-11-03
CPC分类号: H04N21/8166 , G09G5/14 , G09G5/395 , H04N5/44 , H04N5/4401 , H04N5/44508 , H04N11/20 , H04N19/42 , H04N19/436 , H04N19/61 , H04N21/426 , H04N21/42615 , H04N21/42623 , H04N21/42653 , H04N21/4305 , H04N21/431 , H04N21/43632 , H04N21/439 , H04N21/44 , H04N21/443
摘要: An improved audio-visual circuit is provided that includes a transport packet parsing circuit for receiving a transport data packet stream, a CPU circuit for initializing said integrated circuit and for processing portions of said data packet stream, a ROM circuit for storing data, a RAM circuit for storing data, an audio decoder circuit for decoding audio portions of said data packet stream, a video decoder circuit for decoding video portions of said data packet stream, an NTSC/PAL encoding circuit for encoding video portions of said data packet stream, an OSD coprocessor circuit for processing OSD portions of said data packets, a traffic controller circuit moving portions of said data packet stream between portions of said integrated circuit, an extension bus interface circuit, a P1394 interface circuit, a communication coprocessors circuit, an address bus connected to said circuits, and a data bus connected to said circuits.
摘要翻译: 提供了一种改进的视听电路,其包括用于接收传输数据分组流的传输分组解析电路,用于初始化所述集成电路并用于处理所述数据分组流的部分的CPU电路,用于存储数据的ROM电路,RAM 用于存储数据的电路,用于解码所述数据分组流的音频部分的音频解码器电路,用于解码所述数据分组流的视频部分的视频解码器电路,用于对所述数据分组流的视频部分进行编码的NTSC / PAL编码电路, 用于处理所述数据分组的OSD部分的OSD协处理器电路,业务控制器电路,在所述集成电路的部分之间移动所述数据分组流的部分,扩展总线接口电路,P1394接口电路,通信协处理器电路,连接的地址总线 连接到所述电路,以及连接到所述电路的数据总线。
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