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7 条记录 (耗时 0.01 秒)

    Transpose FIR filter architecture
    1.
    发明公开
    Transpose FIR filter architecture 有权
    Transponierte FIR-Filterarchitektur

    公开(公告)号：EP1168615A1

    公开(公告)日：2002-01-02

    申请号：EP01000254.1

    申请日：2001-06-26

    申请人： Texas Instruments Incorporated

    发明人： Kiriaki, Sami

    IPC分类号： H03H17/06 ,  H03H15/00

    CPC分类号： H03H15/00 ,  H03H17/06

    摘要： A novel Finite Impulse Response ("FIR") filter (100) is provided with. A master/slave sample and hold architecture is employed. In this architecture, an input signal (V IN ) is coupled to an input of a master sample and hold circuit (104). At least two slave sample and hold circuits (114, 118) connect to the master output. The slave sample and hold circuits (114, 118) operate at 1/k times the clock rate of the master sample and hold circuit (104), where k equals the number of slave sample and hold circuits (114, 118). A first multiplexer (126) multiplexes the slave outputs together. At least one tap block (129, 179, 207) is coupled to the first multiplexer (126) includes a multiplier (132, 180, 210), a summer (142, 142, 216), at least two slave sample and hold circuits (152, 154, 188, 190, 224, 226) and a second multiplexer (164, 200, 236). The slave sample and hold circuits (152, 154, 188, 190, 224, 226) run at 1/k times the clock speed of the master sample and hold circuit (126).

    摘要翻译： 提供了一种新颖的有限脉冲响应（“FIR”）滤波器（100）。 采用主/从采样和保持架构。 在该结构中，输入信号（VIN）耦合到主采样和保持电路（104）的输入端。 至少两个从站采样和保持电路（114,118）连接到主输出。 从采样和保持电路（114,118）以主采样和保持电路（104）的时钟速率的1 / k倍工作，其中k等于从采样和保持电路（114,118）的数量。 第一多路复用器（126）将从输出端复用在一起。 至少一个抽头块（129,179,207）耦合到第一多路复用器（126），包括乘法器（132,180,210），加法器（142,142,216），至少两个从采样和保持电路 （152,154,188,190,224,226）和第二多路复用器（164,200,236）。 从采样和保持电路（152,154,188,190,224,226）以主采样保持电路（126）的时钟速度的1 / k倍运行。

    Sync detect circuit
    2.
    发明公开
    Sync detect circuit 失效
    Schaltung zum Detektieren eines Synchronisationssignals

    公开(公告)号：EP0851626A2

    公开(公告)日：1998-07-01

    申请号：EP97310518.2

    申请日：1997-12-23

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Staszewski, Bogdan ,  Kiriaki, Sami

    IPC分类号： H04L7/04

    CPC分类号： G11B27/3027 ,  H04L7/042

    摘要： A sync detect circuit is comprised of two serial data registers (40) and (42), each for storing a single word. A plurality of current sources in current source banks (44) and (46) are operable to convert the bits in the stored sync word to a differential current domain. Depending upon the logic state, the currents are added on two lines (50) and (52). When the differential current falls below a predetermined limit, a frame sync signal is generated to latch the next and following words into a data latch (34). These are then transferred out to a system upon the generation of a system data clock.

    摘要翻译： 同步检测电路由两个串行数据寄存器（40）和（42）组成，每个用于存储单个字。 电流源极组（44）和（46）中的多个电流源可操作以将所存储的同步字中的位转换为差分电流域。 根据逻辑状态，电流被加到两条线（50）和（52）上。 当差分电流下降到预定极限以下时，产生帧同步信号，以将下一个和后续的单词锁存到数据锁存器（34）中。 然后在生成系统数据时钟时将这些数据传送到系统。

    Sync detect circuit
    7.
    发明公开
    Sync detect circuit 失效
    电路用于检测同步信号

    公开(公告)号：EP0851626A3

    公开(公告)日：2001-08-22

    申请号：EP97310518.2

    申请日：1997-12-23

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Staszewski, Bogdan ,  Kiriaki, Sami

    IPC分类号： H04L7/04 ,  H04J3/06 ,  G11B27/30

    CPC分类号： G11B27/3027 ,  H04L7/042

    摘要： A sync detect circuit is comprised of two serial data registers (40) and (42), each for storing a single word. A plurality of current sources in current source banks (44) and (46) are operable to convert the bits in the stored sync word to a differential current domain. Depending upon the logic state, the currents are added on two lines (50) and (52). When the differential current falls below a predetermined limit, a frame sync signal is generated to latch the next and following words into a data latch (34). These are then transferred out to a system upon the generation of a system data clock.