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1.发明授权Hybrid data and clock precharging techniques in domino logic circuits minimizes charge sharing during evaluation 有权混合传票技术在多米诺逻辑电路的数据和时钟，这在评价期间减少的电荷分布
公开(公告)号：EP0954101B1
公开(公告)日：2006-11-02
申请号：EP99201372.2
申请日：1999-04-29
IPC分类号： H03K19/096 , H03K19/003
CPC分类号： H03K19/0963
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2.发明公开Hybrid data and clock precharging techniques in domino logic circuits minimizes charge sharing during evaluation 有权混合传票技术在多米诺逻辑电路的数据和时钟，这在评价期间减少的电荷分布
公开(公告)号：EP0954101A2
公开(公告)日：1999-11-03
申请号：EP99201372.2
申请日：1999-04-29
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A domino logic circuit (400) includes a precharge device (101) precharging a precharge node (110) during a precharge phase and a logic block (121, 123, 125, 127, 129) receiving plural input signals (A, B, C, D, E) to conditionally discharge the precharge node. In this improvement a second precharge device (155) precharges an intermediate node (122) when a particular input signal (E) controls its corresponding logic device to be nonconducting. The intermediate node precharged by this second precharge device may be any intermediate node including the last in a serial chain from the precharge node. This second precharge device may be used with a third precharge device (114) according to the prior art which precharges the intermediate node during the precharge phase. This domino logic circuit may be used with another precharge device (150) controlled by a second input signal (D) different from the first input signal. This additional precharge device may be used to precharge the same intermediate node or another intermediate node. If the input signal controlling the second precharge device is unconstrained, then the circuit preferably includes a clock controlled precharge device to precharge the intermediate node during the precharge phase and a discharge control device disposed between said logic block and ground preventing discharge during the precharge phase. Alternatively, the input signal may be clocked and guaranteed low during the precharge phase. In this case, the clocked precharge of the intermediate node and the discharge control device are optional.
摘要翻译： 多米诺逻辑电路（400）包括预充电装置（101）预充电期间预充电阶段接收多个输入信号（A，B，C的预充电节点（110）和一个逻辑块（121，123，125，127，129） ，D，E），以有条件地放电的预充电节点。 在这种改进的第二预充电装置（155）在预充电中间节点（122），当一个特定的输入信号（E）控制其相应的逻辑器件被导通。 由该第二预充电装置预充电的中间节点可以是包括在从所述预充电节点的串行链中的最后的任何中间节点。 该第二预充电装置可与第三预充电装置（114），雅丁现有技术哪个预充电期间，预充电阶段的中间节点使用。 此多米诺逻辑电路可以与由第二输入信号（D）从第一输入信号中的不同控制的另一预充电设备（150）一起使用。 该附加的预充电装置可用于预充电相同的中间节点或另一中间节点。 如果输入信号控制第二预充电装置不受约束，那么电路最好包括一个时钟控制的预充电装置预充电阶段期间和预充电阶段期间，所述逻辑块与地面防止放电之间设置的放电控制装置，以预充电中间节点。 可替换地，输入信号可以被定时，并在预充电阶段保证低。 在这种情况下，中间节点的时钟预充电和放电控制装置是可选的。
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3.发明公开Hybrid data and clock precharging techniques in domino logic circuits minimizes charge sharing during evaluation 有权混合传票技术在多米诺逻辑电路的数据和时钟，这在评价期间减少的电荷分布
公开(公告)号：EP0954101A3
公开(公告)日：2000-06-14
申请号：EP99201372.2
申请日：1999-04-29
IPC分类号： H03K19/096 , H03K19/003
CPC分类号： H03K19/0963
摘要： A domino logic circuit (400) includes a precharge device (101) precharging a precharge node (110) during a precharge phase and a logic block (121,123,125,127,129) receiving plural input signals (A,B,C,D,E) to conditionally discharge the precharge node. In this improvement a second precharge device (150) precharges an intermediate node (122) when a particular input signal (E) controls its corresponding logic device to be nonconducting. The intermediate node precharged by this second precharge device may be any intermediate node including the last in a serial chain from the precharge node. This second precharge device may be used with a third precharge device (114) according to the prior art which precharges the intermediate node during the precharge phase. This domino logic circuit may be used with another precharge device (155) controlled by a second input signal (D) different from the first input signal. This additional precharge device may be used to precharge the same intermediate node or another intermediate node. If the input signal controlling the second precharge device is unconstrained, then the circuit preferably includes a clock controlled precharge device to precharge the intermediate node during the precharge phase and a discharge control device disposed between said logic block and ground preventing discharge during the precharge phase. Alternatively, the input signal may be clocked and guaranteed low during the precharge phase. In this case, the clocked precharge of the intermediate node and the discharge control device are optional.
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