公开(公告)号：EP0817199A2

公开(公告)日：1998-01-07

申请号：EP97110765.1

申请日：1997-07-01

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： van der Wagt, Jan P.

IPC分类号： G11C11/36

CPC分类号： B82Y10/00 ,  G11C11/36 ,  G11C2211/5614

摘要： A memory system is organized as a matrix including a memory cell at each intersection of a bit line with write and read word lines Each memory cell comprises a first FET 20 having its gate coupled to a write word line and its drain coupled to a bit line, a second FET 22 having its source coupled to the bit line and its drain coupled to a read word line, and first and second negative resistance devices 24,26 coupled in series between a supply voltage and a substrate voltage, the common point SN of the series-connected negative resistance devices being coupled to the source of the first FET and to the gate of the second FET. Preferably, the first FET 20 is a p-channel device, the second FET 22 is an n-channel device, and the first and second negative resistance devices 24,26 are RTDs. In a second embodiment, a memory system has a memory cell at each intersection of a bit line with a word line. The memory cell comprises an FET having its gate coupled to a word line and one of its drain and source electrodes coupled to a bit line, first and second negative resistance devices 44,46 coupled in series between a supply voltage and a substrate voltage, the common point SN of the series-connected negative resistance devices being coupled to the other of the drain and source electrodes, and a capacitance 48 coupled between the common point of the series-connected negative resistance devices.

公开(公告)号：EP0844617A3

公开(公告)日：1999-06-16

申请号：EP97120551.3

申请日：1997-11-24

申请人： Texas Instruments Incorporated

发明人： Blake, Terence G.W. ,  van der Wagt, Jan P.

IPC分类号： G11C8/00 ,  G11C11/36 ,  G11C11/38

CPC分类号： B82Y10/00 ,  G11C8/16 ,  G11C11/38 ,  G11C2211/5614

摘要： A two-port memory cell includes a bistable latch of two series connected resonant tunnel diodes (RTDs) 34, 38 connected between supply (+Pwr) and substrate (-Pwr) voltages, the common node 36 of the two RTDs being coupled to both the reading and writing functions of the cell. The writing function is achieved by a field effect pass transistor 30 whose active electrodes 25, 28 are tied between the common node of the RTDs and the bit writing bus WB and whose gate 26 is tied to the digital memory word writing bus WW. The reading function is achieved with a sense amplifier n-channel transistor 46 with the source tied to the negative power supply, the gate 40 tied to the common node 36 of the RTDs and the drain 42 tied to an electrode 48 of an n-channel pass transistor 53 which connects the sense amplifier drain 42 to the read bit line RB depending on the gate voltage of the pass transistor 53 whose gate 50 is tied to the read word line RW.

公开(公告)号：EP0844617A2

公开(公告)日：1998-05-27

申请号：EP97120551.3

申请日：1997-11-24

申请人： Texas Instruments Incorporated

发明人： Blake, Terence G.W. ,  van der Wagt, Jan P.

IPC分类号： G11C8/00 ,  G11C11/36 ,  G11C11/38

CPC分类号： B82Y10/00 ,  G11C8/16 ,  G11C11/38 ,  G11C2211/5614

摘要： A two-port memory cell includes a bistable latch of two series connected resonant tunnel diodes (RTDs) 34, 38 connected between supply (+Pwr) and substrate (-Pwr) voltages, the common node 36 of the two RTDs being coupled to both the reading and writing functions of the cell. The writing function is achieved by a field effect pass transistor 30 whose active electrodes 25, 28 are tied between the common node of the RTDs and the bit writing bus WB and whose gate 26 is tied to the digital memory word writing bus WW. The reading function is achieved with a sense amplifier n-channel transistor 46 with the source tied to the negative power supply, the gate 40 tied to the common node 36 of the RTDs and the drain 42 tied to an electrode 48 of an n-channel pass transistor 53 which connects the sense amplifier drain 42 to the read bit line RB depending on the gate voltage of the pass transistor 53 whose gate 50 is tied to the read word line RW.

摘要翻译： 双端口存储单元包括连接在电源（+ Pwr）和衬底（-Pwr）电压之间的两个串联连接的谐振隧道二极管（RTD）34,38的双稳态锁存器，两个RTD的公共节点36耦合到两个 单元的读写功能。 写入功能通过场效应晶体管30实现，其有源电极25,28被连接在RTD的公共节点和位写入总线WB之间，其栅极26被连接到数字存储器字写入总线WW。 读取功能通过读出放大器n沟道晶体管46实现，其源极连接到负电源，栅极40连接到RTD的公共节点36，漏极42连接到n沟道的电极48 将读出放大器漏极42连接到读取位线RB的晶体管53，其取决于栅极50被连接到读取字线RW的通过晶体管53的栅极电压。

公开(公告)号：EP0817199B1

公开(公告)日：2002-11-27

申请号：EP97110765.1

申请日：1997-07-01

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： van der Wagt, Jan P.

IPC分类号： G11C11/36

CPC分类号： B82Y10/00 ,  G11C11/36 ,  G11C2211/5614

公开(公告)号：EP0817199A3

公开(公告)日：1999-10-13

申请号：EP97110765.1

申请日：1997-07-01

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： van der Wagt, Jan P.

IPC分类号： G11C11/36

CPC分类号： B82Y10/00 ,  G11C11/36 ,  G11C2211/5614

摘要： A memory system is organized as a matrix including a memory cell at each intersection of a bit line with write and read word lines Each memory cell comprises a first FET 20 having its gate coupled to a write word line and its drain coupled to a bit line, a second FET 22 having its source coupled to the bit line and its drain coupled to a read word line, and first and second negative resistance devices 24,26 coupled in series between a supply voltage and a substrate voltage, the common point SN of the series-connected negative resistance devices being coupled to the source of the first FET and to the gate of the second FET. Preferably, the first FET 20 is a p-channel device, the second FET 22 is an n-channel device, and the first and second negative resistance devices 24,26 are RTDs. In a second embodiment, a memory system has a memory cell at each intersection of a bit line with a word line. The memory cell comprises an FET having its gate coupled to a word line and one of its drain and source electrodes coupled to a bit line, first and second negative resistance devices 44,46 coupled in series between a supply voltage and a substrate voltage, the common point SN of the series-connected negative resistance devices being coupled to the other of the drain and source electrodes, and a capacitance 48 coupled between the common point of the series-connected negative resistance devices.

摘要翻译： 存储器系统被组织为包括位线与写入和读取字线的每个交叉处的存储器单元的矩阵。每个存储器单元包括第一FET 20，其栅极耦合到写入字线并且其漏极耦合到位线 ，其源极耦合到位线的第二FET 22及其耦合到读取字线的漏极以及串联耦合在电源电压和衬底电压之间的第一和第二负电阻器件24,26，公共点SN 串联的负电阻器件耦合到第一FET的源极和第二FET的栅极。 优选地，第一FET 20是p沟道器件，第二FET 22是n沟道器件，第一和第二负电阻器件24,26是RTD。 在第二实施例中，存储器系统在位线与字线的每个交叉处具有存储单元。 存储单元包括其栅极耦合到字线并且其漏极和源电极中的一个耦合到位线的FET，在电源电压和衬底电压之间串联耦合的第一和第二负电阻器件44,46， 串联负电阻器件的公共点SN耦合到漏极和源电极中的另一个，以及耦合在串联连接的负电阻器件的公共点之间的电容48。