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23 条记录 (耗时 0.012 秒)

    PROGRAMMABLE MOLECULAR DEVICE
    1.
    发明公开
    PROGRAMMABLE MOLECULAR DEVICE 审中-公开
    可编程分子器件

    公开(公告)号：EP1319231A1

    公开(公告)日：2003-06-18

    申请号：EP01959175.9

    申请日：2001-07-25

    申请人： Wm. MARSH RICE UNIVERSITY

    发明人： TOUR, James, M. ,  VAN ZANDT, Bill ,  HUSBAND, Christopher ,  HUSBAND, Summer

    IPC分类号： G11C11/00 ,  H03K4/90

    CPC分类号： H03K19/177 ,  B82Y10/00 ,  B82Y30/00 ,  G06N3/002 ,  G11C11/36 ,  G11C13/0014 ,  G11C13/025 ,  G11C2213/81 ,  H01L51/0595

    摘要： A programmable molecular device (10) is provided that includes a random nano-network that includes a plurality of molecular circuit components. Preferred molecular circuit components include molecular diodes that exhibit negative differential resistance. A method of programming the molecular device may include configuring the molecular components. Configuring a molecular component may include applying a voltage across input and output leads connected to the nano-networks. The voltage may be determined according to a self-adapting algorithm that programs the device to function, for example, as a logic unit or a memory unit. A molecular computer may include a plurality of programmable molecular devices (10) that are interconnected by metallic wires (14).

    Display
    3.
    发明公开
    Display 审中-公开
    浏览量

    公开(公告)号：EP2437247A1

    公开(公告)日：2012-04-04

    申请号：EP10185569.0

    申请日：2010-10-01

    申请人： Nederlandse Organisatie voor Toegepast -Natuurwetenschappelijk Onderzoek TNO ,  IMEC vzw

    发明人： Gelingk, Gerwin Hermanus

    IPC分类号： G09G3/32 ,  G11C11/22 ,  H01L27/28 ,  H01L51/05

    CPC分类号： G09G3/3216 ,  G11C11/36

    摘要： A display comprising: an array of pixel units, each comprising a light emitting diode (LED) programmable between a first state in which it emits light when forward biased above its turn-on voltage and a second state in which it does not emit light when forward biased above its turn-on voltage; an addressing unit by which the pixel units are addressed; and a controller operable to control the addressing unit to apply, in a first phase, drive voltages across the LEDs which program their state, and in a second phase, drive voltages across the LEDs above their turn-on voltages.

    摘要翻译： 一种显示器，包括：像素单元阵列，每个像素单元包括可在第一状态之间可编程的发光二极管（LED），在所述第一状态下，当所述发光二极管在正向偏压高于其导通电压时发光并且在第二状态下不发光， 正向偏压高于其导通电压; 用于寻址像素单元的寻址单元; 以及控制器，其可操作以控制所述寻址单元在第一阶段中施加编程其状态的LED两端的驱动电压，并且在第二阶段中，跨越所述LED的驱动电压高于其导通电压。

    Reading memory cells
    4.
    发明公开
    Reading memory cells 有权
    Lesen von Speicherzellen

    公开(公告)号：EP1225587A3

    公开(公告)日：2003-04-23

    申请号：EP02250092.0

    申请日：2002-01-08

    申请人： Hewlett-Packard Company

    发明人： Hogan, Josh N.

    IPC分类号： G11C7/00 ,  G11C11/16 ,  G11C11/34 ,  G11C17/06 ,  G11C17/14

    CPC分类号： G11C13/0004 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/36 ,  G11C13/004 ,  G11C17/06 ,  G11C2213/72

    摘要： In a memory cell reading method, a memory cell (12) is addressed, an input signal is applied to the addressed memory cell over a range of values, and the state of the memory cell is read based upon a discontinuity in a sensed electrical response to the applied input signal values. The state of the cell (12) is preferably read based upon a discontinuity in the sensed electrical response over a range of applied input signal values encompassing a rail voltage value, for example within one or more diode drops of the rail voltage value.

    摘要翻译： 描述了能够以更高精度确定存储器单元的状态的系统和方法。 在一个存储单元感测方法中，存储单元被寻址，输入信号在一个值的范围上被施加到寻址的存储器单元，并且基于对应用的感测电响应的不连续性来读取存储单元的状态 输入信号值。

    Logic circuitry
    6.
    发明公开
    Logic circuitry 失效
    Logische Schaltung。

    公开(公告)号：EP0225698A1

    公开(公告)日：1987-06-16

    申请号：EP86307871.3

    申请日：1986-10-10

    申请人： FUJITSU LIMITED

    发明人： Yokoyama, Naoki ,  Mori, Toshihiko

    IPC分类号： G11C11/34 ,  G11C11/56 ,  H03K3/36 ,  H03K23/00 ,  H03K29/00

    CPC分类号： B82Y10/00 ,  G11C11/34 ,  G11C11/36 ,  G11C11/39 ,  G11C11/56 ,  G11C2211/5614 ,  H03K3/36 ,  H03K23/00

    摘要： Logic circuitry includes a resonant-tunneling transistor (11) including a superlattice containing at least one quantum well layer, and a constant current source (V CC1 ,12) operatively connected between a base and an emitter of the transistor (11) and supplying a constant current to said base. The transistor (11) has a differential negative-resistance characteristic with at least one resonant point (RP) in a relationship between a current (I B ) flowing in the base and a voltage (V B ) between the base and emitter, and having at least two stable base current values (A,B) at both sides of the resonant point (RP) on the characteristic, defined by the changeable base emitter voltage (V BE ). By supplying the base·emitter voltage (V BE ) having an amplitude of at least two amplitudes corresponding to the stable base current values (A,B), the transistor (11) holds data corresponding to the base·emitter voltage (V BE ).
    The above circuitry may be applied to a memory cell (1) and a frequency divider.
    The resonant-tunneling transistor (11) may be a resonant-tunneling hot electron transistor (RHET) or a resonant-tunneling bipolar transistor (RBT).

    摘要翻译： 逻辑电路包括谐振隧穿晶体管（11），其包括含有至少一个量子阱层的超晶格和可操作地连接在晶体管（11）的基极和发射极之间的恒流源（VCC1,12），并提供恒定的 目前到该基地。 晶体管（11）具有差分负电阻特性，其具有在基极中流动的电流（IB）与基极和发射极之间的电压（VB）之间的关系中的至少一个谐振点（RP），并且至少具有 在谐振点（RP）两侧的两个稳定的基极电流值（A，B）对特性的影响，由可变的基极发射极电压（VBE）定义。 通过提供具有对应于稳定的基极电流值（A，B）的至少两个幅度的幅度的基极发生器电压（VBE），晶体管（11）保持对应于基极发生器电压（VBE）的数据。 上述电路可以应用于存储器单元（1）和分频器。 谐振隧穿晶体管（11）可以是谐振隧道热电子晶体管（RHET）或谐振隧穿双极晶体管（RBT）。

    Improvements in or relating to electronic circuits
    10.
    发明公开
    Improvements in or relating to electronic circuits 失效
    Verbesserungen betreffend elektronische Schaltungen

    公开(公告)号：EP0817199A3

    公开(公告)日：1999-10-13

    申请号：EP97110765.1

    申请日：1997-07-01

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： van der Wagt, Jan P.

    IPC分类号： G11C11/36

    CPC分类号： B82Y10/00 ,  G11C11/36 ,  G11C2211/5614

    摘要： A memory system is organized as a matrix including a memory cell at each intersection of a bit line with write and read word lines Each memory cell comprises a first FET 20 having its gate coupled to a write word line and its drain coupled to a bit line, a second FET 22 having its source coupled to the bit line and its drain coupled to a read word line, and first and second negative resistance devices 24,26 coupled in series between a supply voltage and a substrate voltage, the common point SN of the series-connected negative resistance devices being coupled to the source of the first FET and to the gate of the second FET. Preferably, the first FET 20 is a p-channel device, the second FET 22 is an n-channel device, and the first and second negative resistance devices 24,26 are RTDs. In a second embodiment, a memory system has a memory cell at each intersection of a bit line with a word line. The memory cell comprises an FET having its gate coupled to a word line and one of its drain and source electrodes coupled to a bit line, first and second negative resistance devices 44,46 coupled in series between a supply voltage and a substrate voltage, the common point SN of the series-connected negative resistance devices being coupled to the other of the drain and source electrodes, and a capacitance 48 coupled between the common point of the series-connected negative resistance devices.

    摘要翻译： 存储器系统被组织为包括位线与写入和读取字线的每个交叉处的存储器单元的矩阵。每个存储器单元包括第一FET 20，其栅极耦合到写入字线并且其漏极耦合到位线 ，其源极耦合到位线的第二FET 22及其耦合到读取字线的漏极以及串联耦合在电源电压和衬底电压之间的第一和第二负电阻器件24,26，公共点SN 串联的负电阻器件耦合到第一FET的源极和第二FET的栅极。 优选地，第一FET 20是p沟道器件，第二FET 22是n沟道器件，第一和第二负电阻器件24,26是RTD。 在第二实施例中，存储器系统在位线与字线的每个交叉处具有存储单元。 存储单元包括其栅极耦合到字线并且其漏极和源电极中的一个耦合到位线的FET，在电源电压和衬底电压之间串联耦合的第一和第二负电阻器件44,46， 串联负电阻器件的公共点SN耦合到漏极和源电极中的另一个，以及耦合在串联连接的负电阻器件的公共点之间的电容48。