公开(公告)号：EP0471723B1

公开(公告)日：1996-01-31

申请号：EP90907199.5

申请日：1990-05-02

申请人： THE SECRETARY OF STATE FOR DEFENCE IN HER BRITANNIC MAJESTY'S GOVERNMENT OF THE UNITED KINGDOM OF GREAT BRITAIN AND NORTHERN

发明人： McWHIRTER, John, Graham ,  WARD, Jeremy, Stuart ,  KNOWLES, Simon, Christian

IPC分类号： G06F7/544 ,  G06F15/76

CPC分类号： G06F15/8046 ,  G06F7/5443 ,  G06F17/16 ,  G06F2207/3892

摘要： A digital processor (10) for two's complement computations incorporates an array (12*) of multiplier cells (12) each having the one-bit gated full adder logic function. The array (12*) has nearest-neighbour connections (16, 18, 20) containing clock-activated latches (42, 44, 50) for bit propagation. On each clock cycle, the cells (12) receive input data, carry and cumulative sum bits. Each cell (12) adds the carry and cumulative sum bits to the product of the data bit and a respective coefficient digit associated with the relevant cell (12). Data bits pass along array rows and sum bits accumulate in cascade down array columns. Carry bits are recirculated. Each coefficient digit is expressed as a sign bit and at least one magnitude bit consisting of or including a level bit. Each cell (12) includes multiplicative gating means (58, 62) responsive to the sign and level bits, and carry feedback means (60, 66) responsive to a least significant data bit flag to substitute the sign bit for a carry feedback bit. Each coefficient digit may include an additional magnitude bit expressed as a shift bit and employed to select multiplicand data bit significance, the gating means (58, 62) being responsive to flag bits to eliminate unwanted sign extension bit products. The processor (10 or 200) may include accumulating means (14 or 214) incorporating gates (90, 98 or 292, 298, 336) responsive to flag bits and arranged to eliminate unwanted result sign extension bits.

摘要翻译： 用于二进制补码计算的数字处理器（10）包括每个具有一位门控全加器逻辑功能的乘法器单元（12）的阵列（12 *）。 阵列（12 *）具有包含用于比特传播的时钟激活锁存器（42,44,50）的最近邻居连接（16,18,20）。 在每个时钟周期中，单元（12）接收输入数据，进位和累加和位。 每个单元（12）将进位和累加和位添加到数据位和与相关单元（12）相关联的相应系数位的乘积。 数据位沿阵列行传递，总和位在级联向下阵列列中累加。 进位是循环的。 每个系数数字被表示为一个符号位和至少一个由一个电平位组成或包括一个电平位的幅度位。 每个单元（12）包括响应于符号和电平位的乘法门控装置（58,62），并且携带响应于最低有效数据位标志的反馈装置（60,66）以将符号位替换为进位反馈位。 每个系数数字可以包括表示为移位位并用于选择被乘数据位重要性的附加幅度位，门控装置（58,62）响应于标志位来消除不想要的符号扩展位产品。 处理器（10或200）可以包括累加装置（14或214），该装置响应于标志位而并入门（90,98或292,298,336）并且被安排成消除不想要的结果符号扩展位。