公开(公告)号：EP0839408A4

公开(公告)日：1998-08-19

申请号：EP96923666

申请日：1996-07-05

Applicant: TRANSWITCH CORP

Inventor： BARTHOLOMAY WILLIAM G ,  PARRELLA EUGENE L ,  UPP DANIEL C ,  ICHIBA MIKIO S

IPC: G06F1/18 ,  G06F3/00 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/094

CPC classification number: H03K19/018557 ,  H03K19/09429

Abstract: Circuit board insertion circuitry is used in conjunction with a staggered electrical connector (not shown). The insertion circuitry includes an isolated circuit (B1 and M2) which receives a high system voltage upon first stage contact between the card (100) and a high voltage bus (40), and uses that high system voltage to tristate the output of a transceiver (10) on the circuit board (100) prior to second stage contact being made between the transceiver (10) and the backplane data bus (20). Override circuitry (15) for overriding the tristating effects of the isolating circuit is provided such that when the bias circuit (15) which controls the transceiver output is properly powered, the bias circuit will control the transceiver output, and not the isolated circuit. Power fault isolation is also provided by a relatively large resistor (R1) and a Schottky diode (D1).

Abstract translation: 电路板插入电路与交错式电连接器（未示出）结合使用。 插入电路包括隔离电路（B1和M2），隔离电路在卡（100）和高压总线（40）之间的第一级接触时接收高系统电压，并且使用该高系统电压来使收发器的输出三态 （10）与所述底板数据总线（20）之间的第二级接触之前，在所述电路板（100）上安装所述电路板（10）。 提供用于超控隔离电路的三态效应的覆盖电路（15），使得当控制收发器输出的偏置电路（15）被适当地加电时，偏置电路将控制收发器输出而不是隔离电路。 电源故障隔离还由一个相对较大的电阻（R1）和一个肖特基二极管（D1）提供。

公开(公告)号：EP1344355A4

公开(公告)日：2007-02-21

申请号：EP01985971

申请日：2001-11-20

Applicant: TRANSWITCH CORP

Inventor： ROY SUBHASH C ,  DAS SANTANU ,  UPP DANIEL C ,  LIPP WILLIAM B ,  VIJ JITENDER K ,  RENAULT MICHAEL M ,  CARTER FREDERICK R ,  RAMCHANDANI RAJEN S ,  BENOIT STEVEN E ,  TOEBES DAVID K

IPC: H04J3/00 ,  H04J3/16 ,  H04L20060101 ,  H04L12/54 ,  H04L12/64 ,  H04L12/70 ,  H04L12/931 ,  H04L29/06 ,  H04Q3/52 ,  H04Q11/04

CPC classification number: H04J3/1617 ,  H04L12/5601 ,  H04L12/6402 ,  H04L49/606 ,  H04L2012/5627 ,  H04L2012/6413 ,  H04Q11/0478

Abstract: A network switch includes at least one port processor (10) and at least one switch element (100). The port processor (10) has an SONET OC-x interface (12), a UTOPIA interface (44), and an interface to the switch element (100). The port processor (10) has a total I/O bandwidth equivalent to an OC-48, and the switch element (100) has 12x12 ports for a total bandwidth of 30 Gbps. A data frame of 9 rows by 1700 slots is used to transport ATM, TDM, and Packet data. Each frame is transmitted in 125 microseconds. Each slot includes a 4-bit tag plus a 4-byte payload. The last twenty slots of the frame are reserved for link overhead. For ATM and packet data, a PDU of 16 slots is defined for a 64-bytes payload. The PDUs are self-routed through the switch with a 28-bit routing tag. Bandwidth is arbitrated among ATM and Packet connections while maintaining TDM timing.

公开(公告)号：EP0616744A4

公开(公告)日：1995-03-01

申请号：EP93900922

申请日：1992-12-08

Applicant: TRANSWITCH CORP

Inventor： UPP DANIEL C ,  WOLVAVER DAN H

IPC: G06F5/06 ,  H04J3/00 ,  H04J3/07 ,  H04J3/16 ,  H04L7/02 ,  H04L7/00 ,  H04L25/36

CPC classification number: G06F5/06 ,  G06F2205/061 ,  G06F2205/123 ,  H04J3/076 ,  H04J3/1611

Abstract: A digital clock dejitter circuit includes a RAM (20) for receiving an incoming gapped signal (14a), a digital, fractional RAM fullness gauge (30) for tracking the average input and output rates to and from the RAM and for generating therefrom a control indication, and a controllable digital frequency generator (40) for receiving a fast clock signal and the control indication, and for providing therefrom a substantially jitter-free clock signal at the same nominal rate as the incoming gapped signal. The RAM fullness gauge (30) comprises write (54) and read (56) counters which track the movement of data into and out of the RAM, and a subtractor (58) for taking the difference of the counters to obtain the integer value of the RAM depth. The controllable digital frequency generator (40) comprises an adder (72), a register (74) and a fast clock divider (FCC) (76) which provides the fullness gauge with a fractional digital indication of the RAM depth.

公开(公告)号：EP0724796A4

公开(公告)日：1999-11-24

申请号：EP94929268

申请日：1994-09-20

Applicant: TRANSWITCH CORP

Inventor： UPP DANIEL C

IPC: G06F13/362 ,  H04L12/403 ,  H04L12/56 ,  H04Q11/04

CPC classification number: H04L12/5601 ,  H04L12/403 ,  H04L12/4035 ,  H04L2012/5613 ,  H04L2012/5615 ,  H04L2012/5679 ,  H04Q11/0478

Abstract: An asynchronous data transfer and source traffic control system includes a bus master (100) and a plurality of bus users (112, 114, 116) coupled to a bidirectional data bus (120-128). The bus master (100) provides two clock signals (120, 122) to each bus user (112, 114, 116), a system clock (120) and a frame clock (122). The frame clock designates the start of a frame. A frame format preferably includes fifteen or sixteen system clock cycles, the first of which is designated the request field and the last of which includes a grant field. One or more other cycles may be assigned control and/or routing information and the remainder of the cycles comprise a data field of fixed length. During the request field, any number of bus users (112, 114, 116) may request access which is received by the bus master (100). During the grant field, the bus master (100) grants access to a selected bus user (112, 114, 116) for the entire data portion of the next frame. Which user (112, 114, 116) is granted access to the next frame is determined according to an arbitration algorithm in the bus master (100) which may be unknown to the bus users (112, 114, 116). The asynchronous data transfer and source traffic control system has particular application in accommodating the transfer of the contents of ATM cells used in BISDN systems.

公开(公告)号：EP0559649A4

公开(公告)日：1994-07-27

申请号：EP91915029

申请日：1991-07-26

Applicant: TRANSWITCH CORP

Inventor： PARRUCK BIDYUT ,  UPP DANIEL C

IPC: G06F5/10 ,  G06F5/12 ,  H04J3/06 ,  H04J3/07 ,  H04J3/16 ,  H04L25/05 ,  H04J14/08

CPC classification number: G06F5/12 ,  G06F2205/123 ,  H04J3/0623 ,  H04J3/076 ,  H04J3/1611 ,  H04L25/05 ,  Y10S370/907

Abstract: An apparatus and method for transferring a data payload (SPE) from a first substantially SONET signal into a second substantially SONET signal of different frequency. A circuit (43a) for extracting the SPE bytes from the first SONET signal and sending the bytes, according to a first clock, to a FIFO (60) for storage; a circuit (47a) for obtaining the SPE bytes from the FIFO according to a second clock, for building the SPE into the second substantially SONET signal; and a circuit (70) for comparing the relative byte phases of the first and second clocks. To avoid read/write conflicts in the FIFO, the comparison circuit generates and sends a signal to the extracting circuit (34a) which causes the extracting circuit (34a) to change the byte phase at which bytes are sent to the FIFO. To adjust the SPE for frequency differences between the first and second substantially SONET signals, the comparison circuit (70) sends a signal to the circuit which builds the second SONET signal when the two SONET signals have slipped a byte relative to each other.

公开(公告)号：EP0770292A4

公开(公告)日：1999-04-21

申请号：EP95925401

申请日：1995-06-30

Applicant: TRANSWITCH CORP

Inventor： UPP DANIEL C

IPC: G06F5/10 ,  G06F5/12 ,  H04J3/07 ,  H04J3/22

CPC classification number: G06F5/12 ,  G06F2205/061 ,  G06F2205/126 ,  H04J3/076

Abstract: A two stage desynchronizer (10) is provided to receive a gapped data component of an STS-3C(STM-1) signal and provide therefrom an ungapped DS-4NA (E4) data signal. The first stage (10a) includes a data byte formation block which takes the gapped STS-3C payload data and formulates the data into bytes, a first FIFO (25) which receives the bytes, and a first FIFO read controller (30) which utilizes the STS-3C clock signal and causes bytes of data to be read out according to a schedule which reads bytes eight or nine times out of every ten STS-3C clock cycles. For each row (270 byte times) of the STS-3C frame, either 241 or 242 bytes are read out of the FIFO according to a slightly gapped schedule where the reading of the 242nd byte at least partially depends upon the number of stuffs in the signal and the pointer movements received. The second stage (10b) of the desynchronizer (10) includes a second FIFO (50), a second FIFO fullness measurement block (60), and a VCXO (80). The second FIFO fullness measurement block (60) uses the incoming slightly gapped byte clock and the ungapped DS-4NA output clock as inputs for effectively measuring the relative fullness of the second FIFO (50), and provides a control signal based on the relative fullness.

Abstract translation: 甲两级去同步器被设置成接收STS-3C（STM-1）的信号的带空位的数据成分和从到无缺口DS-4NA（E4）的数据信号提供在那里。 第一级包括一个数据字节形成块这需要跳空STS-3C有效载荷数据，并将数据制定成字节，其接收字节的第一FIFO，以及第一FIFO读控制器，其利用了STS-3C时钟信号，并且使字节 数据的读出雅鼎的时间表，读取字节八分，九次，每十个STS-3C时钟周期。 对于STS-3C帧的每行（270字节倍），无论是241个或242字节的雅丁读出的FIFO的到稍微跳空时间表，其中第242字节的读出至少部分地在取决于东西的数量 接收信号和指针移动。 去同步的第二阶段包括第二FIFO，一个FIFO丰满测量块，和一个VCXO。 在FIFO充满度测量块使用传入略微跳空字节时钟和无缺口DS-4NA输出时钟作为用于有效地测量所述第二FIFO的相对充满度的输入，并且提供基于该相对充满度的控制信号。 控制信号被馈送到压控晶体振荡器（VCXO）哪些基因率无缺口DS-4NA或E4时钟响应于此。

公开(公告)号：EP0579595A4

公开(公告)日：1993-01-22

申请号：EP91901141

申请日：1990-11-16

Applicant: TRANSWITCH CORP

Inventor： UPP DANIEL C

IPC: G06F5/06 ,  H04J3/00 ,  H04J3/07 ,  H04J3/16 ,  H04L7/02

CPC classification number: H04J3/1611 ,  G06F5/06 ,  G06F2205/061 ,  G06F2205/123 ,  H04J3/076

Abstract: Clock dejitter circuits are provided and comprise control circuits (30) for generating a plurality of pulses over a clock cycle, and clock circuits (60) for tracking the speeds of jittered incoming data signal and based on those speeds, and utilizing the plurality of pulses, generating substantially unjittered data signals at the nominal rates of the jittered incoming signals. A control circuit (30) broadly includes a divide by value x-divide by value x+1 circuit (42) which receives a fast input clock signal, a modulus y counter (46), and a count decode (52) for providing z control pulses over the count of y, and a logic gate (56) for taking the outputs from the count decode (52) and controlling the divide block (42) to guarantee that the divide block (42) divides the fast input clock signal by value x q times for every r times the divide block (42) divides the fast input clock signal by value x+1; wherein q plus r equals y, and z equals either q+1 or r+1.

公开(公告)号：EP1360787A4

公开(公告)日：2006-09-13

申请号：EP02714788

申请日：2002-01-23

Applicant: TRANSWITCH CORP

Inventor： SINGH KUMAR SHAKTI ,  GOYAL PAWAN ,  BASAK ARNAB ,  KUMAR VIKAS ,  UPP DANIEL C

IPC: H04J3/06 ,  H04J3/07

CPC classification number: H04J3/076 ,  H04J3/0623

Abstract: Methods for retiming and realigning SONET signals include demultiplexing STS-1 signals from an STS-3 signal, buffering each of the three signals in a FIFO (12), determining the FIFO depth over time (24), determining a pointer leak rate based in part on FIFO depth and also based on the rate of received pointer movements (28). For a 28-bytes deep FIFO, if the depth of a FIFO is 12-16 bytes (12), no pointer leaking is performed. If the depth is 0-4 bytes (12), an immediate positive leak is performed. If the depth is 24-28 (12), an immediate negative leak is performed. If the depth is 5-11 bytes (12) a calculated positive leak is performed. If the depth is 17-23 bytes (12), a calculated negative leak is performed. The calculated leak rates are based on the net number of pointer movements (magnitude of positive and negative movements summed) received every 32 seconds (256,000 frames) (20).

公开(公告)号：EP1400079A4

公开(公告)日：2006-04-05

申请号：EP02734195

申请日：2002-05-06

Applicant: TRANSWITCH CORP

Inventor： UPP DANIEL C

IPC: H03L7/06 ,  H04J3/07 ,  H04L25/00 ,  H04L25/40

CPC classification number: H04J3/076 ,  H03L7/06

Abstract: The desynchronizer (10) of the present invention includes two FIFOs. The first FIFO has two address counters (read and write), an intermediate count register (26), circuitry (for calculating the difference between the write and the intermediate counts and the intermediate and read counts, a logic block for performing pointer leak and other arithmetic functions and digitally controlled oscillator. The second FIFO has read and write counters, a phase-frequency detector (54), and an internal VCO (58) controlled by length measurements of the second FIFO. The desynchronizer (10) receives data bits, pointer movement indications, and stuff indications from a DS-3/E3 demapper and, using the first FIFO, the address counters, etc., removes the low frequency components, including SONET/SDH systemic gapping in order to provide the second FIFO with a DS-3/E3 signal having a high frequency phase modulation. The second FIFO removes the remaining high frequency gapping jitter.

Abstract translation: 本发明的去同步器（10）包括两个FIFO。 第一个FIFO有两个地址计数器（读和写），一个中间计数寄存器（26），电路（用于计算写和中间计数之间的差值以及中间和读计数，一个用于执行指针泄漏的逻辑块和其他 第二FIFO具有读和写计数器，相位频率检测器（54）和由第二FIFO的长度测量控制的内部VCO（58），去同步器（10）接收数据比特， 指针移动指示和来自DS-3 / E3去映射器的填充指示，并且使用第一FIFO，地址计数器等去除低频成分，包括SONET / SDH系统间隔，以便为第二FIFO提供 具有高频相位调制的DS-3 / E3信号，第二个FIFO去除剩余的高频间隙抖动。

公开(公告)号：EP0872056A4

公开(公告)日：1999-10-27

申请号：EP96910692

申请日：1996-03-28

Applicant: TRANSWITCH CORP

Inventor： UPP DANIEL C ,  WOLAVER DAN H

IPC: H04J3/06 ,  H04L12/56 ,  H04Q11/04

CPC classification number: H04J3/0632 ,  H04L2012/5652 ,  H04L2012/5674 ,  H04Q11/0478

Abstract: An SRTS clock recovery apparatus and method are provided. The apparatus broadly includes a controllable destination node clock generator (37) such as a digitally controllable oscillator, a block (36, 38, 40) for generating a local RTS-related value from the destination node clock (37) and the system reference clock (10), and a comparator (50) which compares the incoming RTS-related value to the local RTS-related value to provide a feedback error or control signal which is used to adjust the controllable clock generator (37). If desired, a filter (52) which filters the error signal can be provided in the loop. With the feedback loop as provided, when the destination node clock (37) is faster than the source clock, the error signal will cause the destination node clock (37) to slow, and vice versa.

Abstract translation: 提供了一种SRTS时钟恢复装置和方法。 该装置广泛地包括可控目的地节点时钟发生器，例如数字可控振荡器，用于从目的地节点时钟和系统参考时钟产生本地RTS相关值的块，以及将进入的RTS相关值与 本地RTS相关值提供反馈误差或控制信号，用于调节可控时钟发生器。 如果需要，可以在循环中提供过滤误差信号的滤波器。 使用所提供的反馈环路，当目标节点时钟比源时钟快时，误差信号将导致目的地节点时钟减慢，反之亦然。