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    OPTIMIZED IMPLEMENTATION OF (DE-)INTERLEAVING FOR 3GPP NEW RADIO
    1.
    发明公开
    OPTIMIZED IMPLEMENTATION OF (DE-)INTERLEAVING FOR 3GPP NEW RADIO 审中-实审

    公开(公告)号：EP4358416A3

    公开(公告)日：2024-05-08

    申请号：EP24160345.5

    申请日：2018-11-07

    申请人： Telefonaktiebolaget LM Ericsson (publ)

    发明人： LIU, Qingchao ,  CHEN, Xixian ,  NEZAMI, Yashar

    IPC分类号： H03M13/00 ,  H03M13/11 ,  H03M13/13 ,  H03M13/27

    CPC分类号： H03M13/116 ,  H03M13/2707 ,  H03M13/635 ,  H03M13/6561 ,  H03M13/6569 ,  H03M13/13

    摘要： Apparatuses and methods are disclosed for a communication device associated with a wireless transmission. In one embodiment, a method includes performing one of a low-density parity check, LDPC, decoding process and an LDPC encoding process by loading a set of bits, in parallel, into a plurality of registers, the set of bits being distributed among the plurality of registers; one of de-interleaving and interleaving the loaded set of bits within the plurality of registers by rearranging the loaded set of bits into one of a de-interleaved and an interleaved set of bits; and after the set of bits is rearranged into the one of the de-interleaved and the interleaved set of bits within the plurality of registers, writing the one of the de-interleaved and the interleaved set of bits, in parallel, from the plurality of registers to memory.

    OPTIMIZED IMPLEMENTATION OF (DE-)INTERLEAVING FOR 3GPP NEW RADIO
    4.
    发明公开
    OPTIMIZED IMPLEMENTATION OF (DE-)INTERLEAVING FOR 3GPP NEW RADIO 审中-实审

    公开(公告)号：EP4358416A2

    公开(公告)日：2024-04-24

    申请号：EP24160345.5

    申请日：2018-11-07

    申请人： Telefonaktiebolaget LM Ericsson (publ)

    发明人： LIU, Qingchao ,  CHEN, Xixian ,  NEZAMI, Yashar

    IPC分类号： H03M13/11

    CPC分类号： H03M13/116 ,  H03M13/2707 ,  H03M13/635 ,  H03M13/6561 ,  H03M13/6569 ,  H03M13/13

    摘要： Apparatuses and methods are disclosed for a communication device associated with a wireless transmission. In one embodiment, a method includes performing one of a low-density parity check, LDPC, decoding process and an LDPC encoding process by loading a set of bits, in parallel, into a plurality of registers, the set of bits being distributed among the plurality of registers; one of de-interleaving and interleaving the loaded set of bits within the plurality of registers by rearranging the loaded set of bits into one of a de-interleaved and an interleaved set of bits; and after the set of bits is rearranged into the one of the de-interleaved and the interleaved set of bits within the plurality of registers, writing the one of the de-interleaved and the interleaved set of bits, in parallel, from the plurality of registers to memory.