-
公开(公告)号：EP4155957A1
公开(公告)日：2023-03-29
申请号：EP21306312.6
申请日：2021-09-22
申请人： Thales Dis France SAS , THALES
IPC分类号： G06F13/42 , H04N21/418 , G06F12/14 , G06F13/16 , G06F13/36 , G06F21/44 , G06F21/53 , H04L45/74 , G06F13/40
摘要： The present invention relates to a data processing system (10) comprising :
- a bus interconnect structure (13),
- a slave device (12) coupled to the bus interconnect structure,
- a slave protection unit (15) coupled to the bus interconnect structure,
- a plurality of master devices (11) coupled to the bus interconnect structure,
each master device of said plurality of master devices having a master identifier,
wherein :
- a master device (11) is configured to run concurrently different threads, and, when a thread run by said master device requests access to said slave device, for issuing on the bus interconnect structure an access request comprising its master identifier and a thread identifier assigned to said thread,
- the slave protection unit (15) is configured to grant said thread access to the slave device through the bus interconnect structure after verifying that the master device issuing the request is allowed to access said slave device based on the master identifier of said master device and that the thread is allowed to access said slave device based on the thread identifier of said thread.-
公开(公告)号：EP4405823A1
公开(公告)日：2024-07-31
申请号：EP22789560.4
申请日：2022-09-20
申请人： THALES DIS FRANCE SAS , THALES
IPC分类号： G06F13/42 , H04N21/418 , G06F12/14 , G06F13/16 , G06F13/36 , G06F21/44 , G06F21/53 , H04L45/74 , G06F13/40
CPC分类号： G06F12/1483 , G06F21/44 , G06F21/53 , G06F12/1441 , G06F2212/105220130101
-
-
4.发明公开
公开(公告)号：EP4357957A1
公开(公告)日：2024-04-24
申请号：EP22306579.8
申请日：2022-10-18
CPC分类号： G06F21/74 , G06F9/30145 , G06F21/52 , G06F9/30189 , G06F9/3836
摘要： The present invention relates to a method for securing against physical or logical attacks an execution of a machine language instructions code comprising a plurality of operation codes, said operation codes being defined by a determined instruction set architecture ISA defining for each operation code one or more elementary operations to be performed when executing an instruction corresponding to said operation code,
said method being performed by an electronic system comprising a processor configured for executing instructions in both a non-secure mode of execution and at least one secure mode of execution securing an execution of said instructions against attacks, wherein :
- executing an instruction in said non-secure mode comprises executing, by the processor, only said elementary operations defined in the determined instruction set architecture for the operation code corresponding to this instruction,
- executing an instruction in one of said secure modes comprises triggering, by the processor, an execution of a different set of elementary operations than said elementary operations defined in the determined instruction set architecture for the operation code corresponding to this instruction,
and said method comprising, performed by the processor:
detecting (S1) in said code successive operation codes forming a determined sequence of operation codes called a gadget,
executing (S2) one or more instructions comprised in said code in a secure mode of execution based on said detected gadget.-
公开(公告)号：EP4261679A1
公开(公告)日：2023-10-18
申请号：EP22305537.7
申请日：2022-04-13
摘要： The present invention relates to a method for a secure execution of a first instruction by a processor of an electronic system comprising at least one memory configured to be coupled to the processor, and said processor comprises processor registers (103) and executions units comprising a load and store unit (104a),
said method comprising:
- fetching (S1) said first instruction in an execution pipeline of the processor,
- determining (S2) if said first instruction to be executed is a load instruction to be protected for loading protected data and associated security information from said at least one memory to the processor registers or a store instruction to be protected for storing protected data and associated security information from the processor registers to said at least one memory,
- when said first instruction to be executed is a load instruction to be protected or a store instruction to be protected, executing sequentially by said processor at least a first operation (S4), a second operation (S5) and a third operation (S6), wherein :
• when said first instruction is a load instruction to be protected, said first operation is a load operation for loading said protected data from said at least one memory to said load and store unit, said second operation is a load operation for loading said security information associated to said protected data from said at least one memory to said load and store unit, and said third operation is a write operation for copying said protected data and said associated security information from said load and store unit to the processor registers,
• when said first instruction is a store instruction to be protected, said first operation is a write operation for copying said protected data and said associated security information from the processor registers to said load and store unit, said second operation is a store operation for storing said copied protected data from said load and store unit to said at least one memory and said third operation is a store operation for storing said copied associated security information from said load and store unit to said at least one memory,
said security information associated to protected data being data enabling to transform said protected data into plain data and/or integrity data enabling to verify integrity of said protected data.-
公开(公告)号：EP4184369A1
公开(公告)日：2023-05-24
申请号：EP21306607.9
申请日：2021-11-18
IPC分类号： G06F21/75
摘要： The present invention relates to a method for a secure execution of a first instruction by processing means of an electronic system, comprising :
- fetching (S1) said first instruction in an execution pipeline of the processing means,
- determining (S2) that said first instruction to be executed is an instruction sensitive to a determined attack, wherein said first instruction, when executed by the processing means, causes the processing means to perform a first function,
- selecting (S3), based on said determined attack, from an internal memory of said processing means, at least one second instruction, which, when executed by the processing means, causes the processing means to perform a combination of said first function and a dedicated security countermeasure against said determined attack,
- executing (S4) said selected second instructions instead of said first instruction.-
公开(公告)号：EP4404087A1
公开(公告)日：2024-07-24
申请号：EP23305077.2
申请日：2023-01-23
CPC分类号： G06F21/52 , G06F21/71 , G06F11/1637 , G06F9/30145
摘要： The invention relates to a method for securing a central processing unit pipeline. According to the invention, the method comprises the steps of providing an integrity pipeline supervisor (IPS) comprising a decoder and a checker; providing the integrity pipeline supervisor with the instruction of the computer program; allowing the decoder of the integrity pipeline supervisor to decode the instruction provided to the integrity pipeline supervisor in order to obtain the decoded instruction structure; providing the checker with the structure of the instruction decoded by the decoder of the integrity pipeline supervisor; providing the checker with the structure of the instruction decoded by the decoder of the central processing unit; allowing the checker to compare the structure of the instruction decoded by the decoder of the integrity pipeline supervisor and the structure of the instruction decoded by the decoder of the central processing unit; and allowing an alarm indicator to be triggered if, as a result of the comparison, the checker detects a discrepancy between the structures.
-
8.发明公开
公开(公告)号：EP4372567A1
公开(公告)日：2024-05-22
申请号：EP22306702.6
申请日：2022-11-18
CPC分类号： G06F12/1416 , G06F12/1441 , G06F21/604 , G06F21/78
摘要： A central processing unit and method for modifying its behavior and controlling access to a memory (120) having a plurality of memory locations for storing data values can include address range storage (170) for storing information identifying address ranges for a plurality of regions within the memory, and attribute storage (185) for storing, for each region, attributes where the attributes are linked to security, safety, or functionality during a program execution. The central processing unit further includes configuration logic (150) for configuring addresses and attribute of memory regions during the program execution and one or more execution logic units (150) associating attributes (and optionally metadata) to data processed by the central processing unit when data is accessed by the central processing unit and modifying instruction behaviors based on an instruction type and the attributes associated with the data being processed.
-
公开(公告)号：EP4327216A1
公开(公告)日：2024-02-28
申请号：EP22723138.8
申请日：2022-04-15
-
-
-
-
-
-
-
-
搜索结果
9 条记录 (耗时 0.011 秒)
