公开(公告)号：EP1146423A3

公开(公告)日：2007-12-26

申请号：EP01108430.8

申请日：2001-04-04

申请人： The Boeing Company

发明人： Kohnen, Kirk ,  Chow, Harry ,  Botzong, Bret M.

IPC分类号： G06F11/18

CPC分类号： G06F11/184 ,  G06F11/1679 ,  G06F11/185

摘要： A voted processing system (18) includes at least three processor groupings (20) coupled to a voter (22). Each processor grouping (20) includes a central processing unit (CPU) (24) and a support logic device (28). The CPUs (24) operate synchronously to execute an operating step every clock cycle. Each operating step of each CPU (24) is accomplished in parallel and substantially simultaneously with each other. The support logic devices (28), such as memory controllers or bus interfaces, are coupled to the CPUs (24). The voter (22) is coupled to all of the processor groupings (20). The voter (22) uses redundant voting to detect errors in any one of the processor groupings (20). An error is detected if a minority of the processor groupings (20) disagrees with a majority of the processor groupings (20). When an error is detected, the majority of processor groupings (20) are considered the correct output while the remaining processor groupings (20) are reset (Fig. 2).

公开(公告)号：EP1146423B1

公开(公告)日：2010-01-20

申请号：EP01108430.8

申请日：2001-04-04

申请人： The Boeing Company

发明人： Kohnen, Kirk ,  Chow, Harry ,  Botzong, Bret M.

IPC分类号： G06F11/18

CPC分类号： G06F11/184 ,  G06F11/1679 ,  G06F11/185

公开(公告)号：EP1146423A2

公开(公告)日：2001-10-17

申请号：EP01108430.8

申请日：2001-04-04

申请人： THE BOEING COMPANY

发明人： Kohnen, Kirk ,  Chow, Harry ,  Botzong, Bret M.

IPC分类号： G06F11/18

CPC分类号： G06F11/184 ,  G06F11/1679 ,  G06F11/185

摘要： A voted processing system (18) includes at least three processor groupings (20) coupled to a voter (22). Each processor grouping (20) includes a central processing unit (CPU) (24) and a support logic device (28). The CPUs (24) operate synchronously to execute an operating step every clock cycle. Each operating step of each CPU (24) is accomplished in parallel and substantially simultaneously with each other. The support logic devices (28), such as memory controllers or bus interfaces, are coupled to the CPUs (24). The voter (22) is coupled to all of the processor groupings (20). The voter (22) uses redundant voting to detect errors in any one of the processor groupings (20). An error is detected if a minority of the processor groupings (20) disagrees with a majority of the processor groupings (20). When an error is detected, the majority of processor groupings (20) are considered the correct output while the remaining processor groupings (20) are reset (Fig. 2).

摘要翻译： 投票处理系统（18）包括耦合到选民（22）的至少三个处理器组（20）。 每个处理器组（20）包括中央处理单元（CPU）（24）和支持逻辑设备（28）。 CPU（24）同步工作，以便每个时钟周期执行一个操作步骤。 每个CPU（24）的每个操作步骤彼此并行并且基本上彼此同时地完成。 诸如存储器控制器或总线接口的支持逻辑器件（28）耦合到CPU（24）。 选民（22）耦合到所有处理器组（20）。 选民（22）使用冗余投票来检测任何一个处理器组（20）中的错误。 如果少数处理器组（20）与大多数处理器分组（20）不一致，则检测到错误。 当检测到错误时，大多数处理器组（20）被认为是正确的输出，而剩余的处理器组（20）被复位（图2）。