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公开(公告)号：EP1152537A3
公开(公告)日：2003-04-09
申请号：EP01401067.2
申请日：2001-04-26
摘要： A phase locked loop, comprising: a controllable oscillator (50,20) requiring a control signal having a given bias voltage for generating a clock signal; an integrator (16) for developing the control signal; a source of an external synchronizing signal (HOR. SYNC.); first and second voltage sources (+15 VDC, GND) defining a voltage potential related to the given bias voltage; a first switch (A) coupled to the first and second voltage sources and responsive to the clock signal (CTRL A) for developing a regenerated clock signal having a peak to peak voltage determined by the voltage potential; and, a second switch (B) responsive to the external synchronizing signal (CTRLB) for periodically sampling portions of the regenerated clock signal and coupling the sampled portions to the to the integrator, the sampled portions charging and discharging the integrator to generate the control signal with a large enough magnitude to provide the given bias voltage, said first and second switches (A,B) forming a phase detector.
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公开(公告)号：EP1152537A2
公开(公告)日：2001-11-07
申请号：EP01401067.2
申请日：2001-04-26
摘要： A phase locked loop, comprising: a controllable oscillator (50,20) requiring a control signal having a given bias voltage for generating a clock signal; an integrator (16) for developing the control signal; a source of an external synchronizing signal (HOR. SYNC.); first and second voltage sources (+15 VDC, GND) defining a voltage potential related to the given bias voltage; a first switch (A) coupled to the first and second voltage sources and responsive to the clock signal (CTRL A) for developing a regenerated clock signal having a peak to peak voltage determined by the voltage potential; and, a second switch (B) responsive to the external synchronizing signal (CTRLB) for periodically sampling portions of the regenerated clock signal and coupling the sampled portions to the to the integrator, the sampled portions charging and discharging the integrator to generate the control signal with a large enough magnitude to provide the given bias voltage, said first and second switches (A,B) forming a phase detector.
摘要翻译： 一种锁相环路，包括：可控振荡器（50,20），其需要具有用于产生时钟信号的给定偏置电压的控制信号; 用于开发控制信号的积分器（16）; 外部同步信号源（HOR。SYNC。）; 第一和第二电压源（+ 15VDC，GND）定义与给定偏置电压有关的电压电位; 耦合到第一和第二电压源的第一开关（A），并且响应于时钟信号（CTRL A），用于开发由电压电位确定的峰到峰电压的再生时钟信号; 以及响应于外部同步信号（CTRLB）的周期性采样再生时钟信号的部分并将采样部分耦合到积分器的第二开关（B），采样部分对积分器进行充电和放电以产生控制信号 具有足够大的幅度以提供给定的偏置电压，所述第一和第二开关（A，B）形成相位检测器。
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公开(公告)号：EP1152601A3
公开(公告)日：2003-03-26
申请号：EP01110480.9
申请日：2001-04-27
CPC分类号： H04N5/126
摘要： A horizontal synchronizing system, comprising: a source of a horizontal synchronizing signal (1fH INPUT); a source (20, 28) of first and second higher frequency horizontal drive signals; a phase detector (14) for generating a first control voltage (17) responsive to the horizontal synchronizing signal and the first horizontal drive signal; a source (22, 24) of a second control signal (25); and, a switch (18) for selectively supplying the first control signal to the source of the drive signals for a phase-locked mode of operation at the first higher frequency and supplying the second control signal to the source of the drive signals for a phase-unlocked mode of operation at the second higher frequency.
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4.发明公开Processing of progressive video signals in digital TV receivers 有权在数字Fernsehempfängern的Verigneitung von progressiven Videosignalen
公开(公告)号：EP1069768A2
公开(公告)日：2001-01-17
申请号：EP00114589.5
申请日：2000-07-07
IPC分类号： H04N5/44
CPC分类号： H04N7/012 , H04N5/4401 , H04N5/46 , H04N9/641 , H04N21/440218 , H04N21/4435
摘要： A memory management process (32) for buffering progressive, interlaced, CCIR 601/656 compliant, and MPEG compliant video signals in a video memory that is partitioned into first and second buffers. The process includes identifying the format (36,44) of a received video signal, buffering the received video signal in the video memory in accordance with a standard buffering mode if the video signal is in an interlaced, CCIR 601/656 compliant, or MPEG compliant format, and buffering the received video signal in the video memory in accordance with an override buffering mode (40, 46) if the video signal is in a progressive format such as a 240p signal generated by a game console, VCR, cable text generator, and the like.
摘要翻译： 一种存储器管理过程（32），用于缓冲被划分为第一和第二缓冲器的视频存储器中的逐行，隔行扫描CCIR 601/656兼容和MPEG兼容视频信号。 该过程包括识别接收到的视频信号的格式（36,44），如果视频信号是隔行扫描CCIR 601/656兼容的，则MPEG根据标准缓冲模式缓冲接收到的视频信号，或者MPEG 如果视频信号是逐行格式，例如由游戏控制台，VCR，电缆文本生成器生成的240p信号，则根据超控缓冲模式（40,46），将所接收的视频信号缓冲在视频存储器中 ，等等。
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公开(公告)号：EP1069768B1
公开(公告)日：2004-09-22
申请号：EP00114589.5
申请日：2000-07-07
IPC分类号： H04N5/44
CPC分类号： H04N7/012 , H04N5/4401 , H04N5/46 , H04N9/641 , H04N21/440218 , H04N21/4435
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公开(公告)号：EP1069768A3
公开(公告)日：2002-06-26
申请号：EP00114589.5
申请日：2000-07-07
IPC分类号： H04N5/44
CPC分类号： H04N7/012 , H04N5/4401 , H04N5/46 , H04N9/641 , H04N21/440218 , H04N21/4435
摘要： A memory management process (32) for buffering progressive, interlaced, CCIR 601/656 compliant, and MPEG compliant video signals in a video memory that is partitioned into first and second buffers. The process includes identifying the format (36,44) of a received video signal, buffering the received video signal in the video memory in accordance with a standard buffering mode if the video signal is in an interlaced, CCIR 601/656 compliant, or MPEG compliant format, and buffering the received video signal in the video memory in accordance with an override buffering mode (40, 46) if the video signal is in a progressive format such as a 240p signal generated by a game console, VCR, cable text generator, and the like.
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7.发明公开Horizontal synchronization for digital television receiver 审中-公开Horizontale SynchronizationfürdigitaleFernsehempfänger
公开(公告)号：EP1152601A2
公开(公告)日：2001-11-07
申请号：EP01110480.9
申请日：2001-04-27
IPC分类号： H04N5/08
CPC分类号： H04N5/126
摘要： A horizontal synchronizing system, comprising: a source of a horizontal synchronizing signal (1fH INPUT); a source (20, 28) of first and second higher frequency horizontal drive signals; a phase detector (14) for generating a first control voltage (17) responsive to the horizontal synchronizing signal and the first horizontal drive signal; a source (22, 24) of a second control signal (25); and, a switch (18) for selectively supplying the first control signal to the source of the drive signals for a phase-locked mode of operation at the first higher frequency and supplying the second control signal to the source of the drive signals for a phase-unlocked mode of operation at the second higher frequency.
摘要翻译： 一种水平同步系统，包括：水平同步信号源（1fH INPUT）; 第一和第二较高频率水平驱动信号的源极（20,28）; 相位检测器（14），用于响应于水平同步信号和第一水平驱动信号产生第一控制电压（17）; 第二控制信号（25）的源（22,24）; 以及开关（18），用于选择性地将第一控制信号提供给驱动信号的源，以进行第一较高频率的锁相操作模式，并将第二控制信号提供给驱动信号的源 在第二较高频率下的动态操作模式。
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