公开(公告)号：EP2352228A1

公开(公告)日：2011-08-03

申请号：EP09823625.0

申请日：2009-10-28

申请人： Tokyo Institute of Technology

发明人： MATSUZAWA Akira ,  MIYAHARA Masaya

IPC分类号： H03K5/08 ,  H03M1/36

CPC分类号： H03K5/2481 ,  H03K3/356139 ,  H03K5/249 ,  H03M1/0682 ,  H03M1/204 ,  H03M1/365

摘要： With a comparator and an A/D converter having the comparator, it is possible to problems caused by timing-skew between two clock signals with different polarities, and to enable low-power operation.
To provide a comparator and an A/D converter having the comparator. The comparator includes a differential amplifier circuit section and a differential latch circuit section. A first input voltage signal, a second input voltage signal and a clock signal are inputted to the differential amplifier circuit section. The differential amplifier circuit section operates base on the clock signal to output a first output voltage signal and a second output voltage signal which respectively correspond to the value the input voltage signal and the value of the reference voltage signal and are amplified. The differential latch circuit section operates based on the first and second output voltage signals to keep and output a comparison result between the first input voltage signal and the second input voltage signal.

摘要翻译： 通过比较器和具有比较器的A / D转换器，可能由具有不同极性的两个时钟信号之间的定时偏移引起的问题，并且能够进行低功率操作。 提供具有比较器的比较器和A / D转换器。 比较器包括差分放大器电路部分和差分锁存电路部分。 第一输入电压信号，第二输入电压信号和时钟信号被输入到差分放大器电路部分。 差分放大器电路部分基于时钟信号进行工作，以输出分别对应于输入电压信号的值和参考电压信号的值并被放大的第一输出电压信号和第二输出电压信号。 差分锁存电路部分基于第一和第二输出电压信号进行操作，以保持并输出第一输入电压信号和第二输入电压信号之间的比较结果。