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    DATA COMMUNICATIONS WITH ANALOG-TO-DIGITAL CONVERSION
    1.
    发明公开
    DATA COMMUNICATIONS WITH ANALOG-TO-DIGITAL CONVERSION 审中-公开
    DATENKOMMUNIKATION MIT模拟数字万圣节

    公开(公告)号：EP2993788A1

    公开(公告)日：2016-03-09

    申请号：EP15181940.6

    申请日：2015-08-21

    申请人： NXP B.V.

    发明人： Leong, Frank ,  Hekstra, Andries ,  Koppelaar, Arie ,  Drude, Stefan

    IPC分类号： H03M1/12

    CPC分类号： H03M1/1255 ,  H03M1/00 ,  H03M1/12 ,  H03M1/365

    摘要： Aspects of the preset disclosure are directed to processing an analog signal transmitted during active portions of a duty cycle. As may be implemented in accordance with one or more embodiments, an apparatus includes a high-speed sampling circuit that samples portions of such an analog signal at a first rate corresponding to the active portion of the duty cycle, and stores the sampled portions of the analog signal. A low-speed analog-to-digital converter accesses the stored sampled portions and converts the sampled portions to a digital form at a second rate that is slower than the first rate.

    摘要翻译： 预设公开的方面旨在处理在占空比的有效部分期间发送的模拟信号。 如可以根据一个或多个实施例实现的，装置包括高速采样电路，其以对应于占空比的有效部分的第一速率对这样的模拟信号的部分进行采样，并存储采样部分 模拟信号。 低速模数转换器访问存储的采样部分，并以比第一速率慢的第二速率将采样部分转换成数字形式。

    COMPARATOR AND ANALOG/DIGITAL CONVERTER
    4.
    发明公开
    COMPARATOR AND ANALOG/DIGITAL CONVERTER 审中-公开
    KOMPARATOR UND ANALOG-DIGITAL-WANDLER

    公开(公告)号：EP2352228A1

    公开(公告)日：2011-08-03

    申请号：EP09823625.0

    申请日：2009-10-28

    申请人： Tokyo Institute of Technology

    发明人： MATSUZAWA Akira ,  MIYAHARA Masaya

    IPC分类号： H03K5/08 ,  H03M1/36

    CPC分类号： H03K5/2481 ,  H03K3/356139 ,  H03K5/249 ,  H03M1/0682 ,  H03M1/204 ,  H03M1/365

    摘要： With a comparator and an A/D converter having the comparator, it is possible to problems caused by timing-skew between two clock signals with different polarities, and to enable low-power operation.
    To provide a comparator and an A/D converter having the comparator. The comparator includes a differential amplifier circuit section and a differential latch circuit section. A first input voltage signal, a second input voltage signal and a clock signal are inputted to the differential amplifier circuit section. The differential amplifier circuit section operates base on the clock signal to output a first output voltage signal and a second output voltage signal which respectively correspond to the value the input voltage signal and the value of the reference voltage signal and are amplified. The differential latch circuit section operates based on the first and second output voltage signals to keep and output a comparison result between the first input voltage signal and the second input voltage signal.

    摘要翻译： 通过比较器和具有比较器的A / D转换器，可能由具有不同极性的两个时钟信号之间的定时偏移引起的问题，并且能够进行低功率操作。 提供具有比较器的比较器和A / D转换器。 比较器包括差分放大器电路部分和差分锁存电路部分。 第一输入电压信号，第二输入电压信号和时钟信号被输入到差分放大器电路部分。 差分放大器电路部分基于时钟信号进行工作，以输出分别对应于输入电压信号的值和参考电压信号的值并被放大的第一输出电压信号和第二输出电压信号。 差分锁存电路部分基于第一和第二输出电压信号进行操作，以保持并输出第一输入电压信号和第二输入电压信号之间的比较结果。

    FOLDING CIRCUIT AND ANALOG-TO-DIGITAL CONVERTER
    5.
    发明公开
    FOLDING CIRCUIT AND ANALOG-TO-DIGITAL CONVERTER 有权
    UMLEGESCHALTUNG UND ANALOG- / DIGITALKONVERTER

    公开(公告)号：EP2051382A1

    公开(公告)日：2009-04-22

    申请号：EP07806629.7

    申请日：2007-09-04

    申请人： Sony Corporation

    发明人： OHKAWA, Takeshi ,  ONO, Koichi ,  MATSUURA, Kouji ,  YAMASITA, Yukitosi ,  TOYOMURA, Junji ,  NAKAMURA, Shogo ,  KANAGAWA, Norifumi

    IPC分类号： H03M1/36 ,  H03M1/14

    CPC分类号： H03M1/0863 ,  H03M1/0682 ,  H03M1/141 ,  H03M1/205 ,  H03M1/365

    摘要： A folding circuit and an analog-to-digital converter wherein a response to small signals is improved, a load on a clock signal can be reduced, and the increase of circuit area can be prevented. The circuit includes a reference voltage generating circuit that generates a plurality of differential voltages as reference voltages, and a plurality of amplification circuits that convert differential voltages between the plurality of reference voltages and an analog input voltage to differential currents, and output these differential currents. The output ends of the amplification circuits are alternately connected. Each of the amplification circuit is configured by a differential amplifier circuit having cascode output transistors (145, 146). A switch (144), which is turned on in synchronization with the control clock, is provided between the both sources of the cascode output transistors (145,146).

    摘要翻译： 折叠电路和模数转换器，其中对小信号的响应得到改善，可以减少对时钟信号的负载，并且可以防止电路面积的增加。 电路包括产生多个差分电压作为参考电压的参考电压产生电路，以及将多个参考电压之间的差分电压和模拟输入电压转换为差分电流的多个放大电路，并输出这些差分电流。 放大电路的输出端交替连接。 每个放大电路由具有共源共栅输出晶体管（145,146）的差分放大器电路构成。 在共源共栅输出晶体管（145,146）的两个源之间提供与控制时钟同步导通的开关（144）。

    HIGH-SPEED LOW-DISTORTION ANALOG-TO-DIGITAL CONVERTER
    8.
    发明公开
    HIGH-SPEED LOW-DISTORTION ANALOG-TO-DIGITAL CONVERTER 有权
    具有低失真快速模拟/数字转换器

    公开(公告)号：EP1540825A4

    公开(公告)日：2006-11-22

    申请号：EP03749360

    申请日：2003-09-03

    申请人： BROADCOM CORP

    发明人： JIANG XICHENG ,  WANG ZHENGYU ,  CHANG FRANK

    IPC分类号： H03M1/06 ,  H03M1/66

    CPC分类号： H03M1/0646 ,  G11C27/026 ,  H03M1/0682 ,  H03M1/365

    摘要： An analog to digital converter includes an array (101) of differential input amplifiers (301A, 301B). Each amplifier inputs an input voltage and a corresponding voltage reference, and outputs a differential signal representing a comparison of the input voltage and the corresponding voltage reference. A plurality of latches stores the differential signal from each of the differential input amplifiers. A decoder converts the stored differential signals to N-bit digital output. A first interface amplifier is connected to a first edge amplifier of the array through a first cross point. A second interface amplifier is connected to a second edge amplifier of the array through a second cross point. The first interface amplifier and the second interface amplifier are connected to each other through a third cross point.

    Interpolation circuit having a conversion error correction range for higher-order bits and A/D conversion circuit utilizing the same
    10.
    发明公开
    Interpolation circuit having a conversion error correction range for higher-order bits and A/D conversion circuit utilizing the same 有权
    内插用Korrektionsbereich在高位比特转换错误，A / D转换器电路具有这样的电路

    公开(公告)号：EP1370001A2

    公开(公告)日：2003-12-10

    申请号：EP03253461.2

    申请日：2003-06-03

    申请人： FUJITSU LIMITED

    发明人： Nakamoto, Hiroyuki, c/o Fujitsu Limited

    IPC分类号： H03M1/16

    CPC分类号： H03M1/165 ,  H03M1/365

    摘要： An interpolation circuit for generating interpolated and extrapolated differential voltages from first and second differential input voltages, comprises first (A) and second (B) differential amplifiers for inputting the first and second differential input voltages, respectively, and for generating a differential output voltage respectively between their inverted output terminal (AN, BN) and their respective non-inverted terminal (AP, BP). The interpolation circuit further comprises a first voltage dividing element array (NT1) disposed between the non-inverted output terminals (AP, BP) of the first and second differential amplifiers, and a second voltage dividing element array (NT2) disposed between the inverted output terminals (AN, BN) of the first and second differential amplifiers, so that the interpolated differential voltages are generated from nodes (n1, n2, n3) in the first voltage dividing element array (NT1) and nodes (n4, n5, n6) in the second voltage dividing element array (NT2). The interpolation circuit further comprises a third voltage dividing element array (NT1) disposed between the inverted output terminal (AN) of the first differential amplifier (A) and the non-inverted output terminal (BP) of the second differential amplifier (B), so that at least a pair of extrapolated differential voltages are generated from nodes (n10, n12) in the third voltage dividing element array (NT3).

    摘要翻译： 为内插电路生成插值和从第一和第二差分输入电压外推差分电压，包括：第一（A）和用于分别输入第一和第二差分输入电压，第二（B）差分放大器，以及用于分别产生差分输出电压 反相输出端（AN，BN）和其respectivement非反相端子（AP，BP）之间的。 内插电路还包括在所述反相输出之间设置在第一和第二差分放大器的非反相输出端（AP，BP）之间布置的第一分压元件阵列（NT1），和一个第二分压元件阵列（NT2） 端子与第一和第二差分放大器的（AN，BN），所以没插值差分电压从节点（N1，N2，N3）中的第一分压元件阵列（NT1）和节点生成（N4，N5，N6） 第二分压元件阵列（NT2）英寸 内插电路还包括一第三分压反相输出端的第一差分放大器的（AN）（A）和所述非反相输出端输出第二差分放大器的（BP）（B）之间设置元件阵列（NT1） 所以也至少一对差分外推电压的从第三分压元件阵列（NT3）中的节点（N10，N12）生成。