公开(公告)号：EP4240131A1

公开(公告)日：2023-09-06

申请号：EP22190021.0

申请日：2022-08-11

申请人： United Microelectronics Corp.

发明人： CHEN, Jian-Jhong ,  WU, Yi-Ting ,  WANG, Jen-Yu ,  HUANG, Cheng-Tung ,  YANG, Po-Chun ,  HSIEH, Yung-Ching

IPC分类号： H10N50/10 ,  H10N50/80 ,  H10N50/01 ,  H10B61/00

摘要： A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.

公开(公告)号：EP3890023A1

公开(公告)日：2021-10-06

申请号：EP20171687.5

申请日：2020-04-28

申请人： United Microelectronics Corp.

发明人： WU, Yi-Ting ,  CHEN, Yan-Jou ,  HUANG, Cheng-Tung ,  WANG, Jen-Yu ,  YANG, Po-Chun ,  HSIEH, Yung-Ching ,  CHEN, Jian-Jhong ,  LI, Bo-Chang

IPC分类号： H01L27/22 ,  G11C5/06

摘要： A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.

公开(公告)号：EP3848932A1

公开(公告)日：2021-07-14

申请号：EP20169743.0

申请日：2020-04-16

申请人： United Microelectronics Corp.

发明人： TSENG, Chun-Yen ,  KUO, Yu-Tse ,  CHEN, Chang-Hung ,  WANG, Shu-Ru ,  CHIOU, Ya-Lan ,  HUANG, Chun-Hsien ,  TSAI, Chih-Wei ,  YU, Hsin-Chih ,  WU, Yi-Ting ,  HUANG, Cheng-Tung ,  WANG, Jen-Yu ,  WU, Jhen-Siang ,  YANG, Po-Chun ,  HSIEH, Yung-Ching ,  CHEN, Jian-Jhong ,  LI, Bo-Chang

IPC分类号： G11C11/16 ,  G11C13/00

摘要： A memory includes (n-1) non-volatile cells, (n-1) bit lines and a current driving circuit. Each of the (n-1) non-volatile cells includes a first terminal and a second terminal. An ith bit line of the (n-1) bit lines is coupled to a first terminal of an ith non-volatile cell of the (n-1) non-volatile cells. The current driving circuit includes n first transistors coupled to the (n-1) non-volatile cells.