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公开(公告)号：EP4355064A3
公开(公告)日：2024-07-17
申请号：EP24160422.2
申请日：2020-05-27
发明人： WU, Jia-Rong , CHANG, I-Fan , HUANG, Rai-Min , TSAI, Ya-Huei , WANG, Yu-Ping
CPC分类号： G11C11/161 , H10B61/00 , H10N50/80 , H10N50/01 , H10N50/10
摘要： A method for fabricating semiconductor device includes the steps of: providing a substrate (12) having a logic region (16) and a magnetoresistive random access memory (MRAM) region, forming a magnetic tunneling junction, MTJ (34), on the MRAM region (14), forming a metal interconnection (26, 32, 48, 54) on the MTJ (34), forming a dielectric layer (64, 66, 68) on the metal interconnection (26, 32, 48, 54), patterning the dielectric layer (64, 66, 68) to form openings (70), and forming the blocking layer (60) on the patterned dielectric layer and the metal interconnection (26, 32, 48, 54) and into the openings (70); wherein the blocking layer (60) comprises a second dielectric layer, particularly silicon carbide, silicon carbon nitride, SiCN, or silicon carbo-oxynitride, SiCON.
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公开(公告)号：EP4393279A1
公开(公告)日：2024-07-03
申请号：EP22765063.7
申请日：2022-08-11
发明人： XIE, Ruilong , REZNICEK, Alexander , WANG, Wei , LI, Tao , KANG, Tsung-Sheng
CPC分类号： G11C11/005 , G11C11/161 , G11C13/0004 , H10B61/10
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4.发明公开
公开(公告)号：EP4369883A1
公开(公告)日：2024-05-15
申请号：EP22206549.2
申请日：2022-11-10
发明人： PARKIN, Stuart S.P.
摘要： The present disclosure relates to a Racetrack (RT) memory, comprising a racetrack layer and at least one reading element, wherein the reading element comprises a polarity-reversible Josephson supercurrent diode (= JJ).
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5.发明公开
公开(公告)号：EP4362650A1
公开(公告)日：2024-05-01
申请号：EP22204790.4
申请日：2022-10-31
申请人： Commissariat à l'énergie atomique et aux énergies alternatives , Centre national de la recherche scientifique , Université Grenoble Alpes , Institut Polytechnique de Grenoble
发明人： Fernandes Caçoilo, Nuno-Filipe , Prejbeanu, Ioan-Lucian , Fruchart, Olivier , Dieny, Bernard , Sousa, Ricardo
摘要： The disclosed magnetic tunnel junction (3) includes a synthetic antiferromagnetic free layer structure (30) comprising a magnetic core (32) and a magnetic shell (31), the magnetic core comprising a magnetic layer (321) having an aspect ratio between 0.5 and 2, the magnetic shell surrounding the magnetic core at least partly along its thickness, and the magnetization of the magnetic shell being antiferromagnetically coupled with the magnetization of the magnetic core. A corresponding fabrication method is disclosed as well.
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公开(公告)号：EP3039440B1
公开(公告)日：2024-05-01
申请号：EP14766613.5
申请日：2014-09-03
CPC分类号： G01R33/077 , H10N59/00 , H10N52/101 , H10N52/01
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公开(公告)号：EP3817055B1
公开(公告)日：2024-01-10
申请号：EP20174720.1
申请日：2020-05-14
发明人： WANG, Hui-Lin , HSU, Po-Kai , JHANG, Jing-Yin , CHEN, Hung-Yueh , WANG, Yu-Ping , WU, Jia-Rong , HUANG, Rai-Min , TSAI, Ya-Huei , CHANG, I-Fan
IPC分类号： H10B61/00
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8.发明公开
公开(公告)号：EP4240131A1
公开(公告)日：2023-09-06
申请号：EP22190021.0
申请日：2022-08-11
发明人： CHEN, Jian-Jhong , WU, Yi-Ting , WANG, Jen-Yu , HUANG, Cheng-Tung , YANG, Po-Chun , HSIEH, Yung-Ching
摘要： A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.
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公开(公告)号：EP4401525A3
公开(公告)日：2024-09-25
申请号：EP23200798.9
申请日：2023-09-29
申请人： INTEL Corporation
发明人： SHARMA, Abhishek Anil , GHANI, Tahir , MURTHY, Anand S. , GOMES, Wilfred , RANADE, Pushkar , SUTHRAM, Sagar
CPC分类号： H10B61/10
摘要： Structures having backside capacitors are described. In an example, an integrated circuit structure (200) includes a front side structure (204) including a device layer (206A) having a plurality of select transistors (Xtor), a plurality of metallization layers (208) above the plurality of select transistors, and a plurality of vias (DV) below and coupled to the plurality of select transistors. A backside structure (202) is below the plurality of vias of the device layer. The backside structure includes a memory layer (206B) coupled to the plurality of select transistors by the plurality of vias.
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公开(公告)号：EP4430931A1
公开(公告)日：2024-09-18
申请号：EP22809029.6
申请日：2022-10-21
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