公开(公告)号：EP3852272A1

公开(公告)日：2021-07-21

申请号：EP20151808.1

申请日：2020-01-14

申请人： University College Dublin, National University of Ireland, Dublin

发明人： HU, Yizhe ,  SIRIBURANON, Teerachot ,  STASZEWSKI, Robert Bogdan

IPC分类号： H03L7/099 ,  H03B5/12 ,  H03L7/14 ,  H03L7/10

摘要： The present disclosure relates to a phase-locked loop (PLL) based on a charge-sharing locking technique, capable of both fractional-N and integer-N operation. The PLL comprises a voltage pre-setting stage; an oscillator: a shared capacitive load; and a switching network configured for selectively connecting the voltage pre-setting stage to the shared capacitive load during a voltage pre-setting stage for applying an expectant voltage to the capacitive load. The switching network is being further configured for selectively connecting the capacitive load to the oscillator during a charge-sharing locking stage for correcting a phase error in response to a difference between the expected voltage of the capacitor and the voltage of the oscillator. Frequency-tracking and waveform-learning stages are also provided for maintaining PVT (process, voltage, temperature) robustness and for suppressing fractional-N spur, respectively.