公开(公告)号：EP2997478B1

公开(公告)日：2019-03-13

申请号：EP14891591.1

申请日：2014-11-26

申请人： VIA Alliance Semiconductor Co., Ltd.

发明人： PARKS, Terry ,  EDDY, Colin ,  MOHAN, Viswanath ,  BUNDA, John, D.

IPC分类号： G06F12/10 ,  G06F12/1027 ,  G06F12/109

公开(公告)号：EP2972797B1

公开(公告)日：2018-04-04

申请号：EP14880052.7

申请日：2014-12-12

申请人： VIA Alliance Semiconductor Co., Ltd.

发明人： HOOKER, Rodney, E. ,  PARKS, Terry ,  BUNDA, John, D.

IPC分类号： G06F9/38 ,  G06F9/44 ,  G06F9/46

CPC分类号： G06F9/46 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3844 ,  G06F9/3851 ,  G06F9/4403

摘要： A microprocessor includes a predicting unit having storage for holding a prediction history of characteristics of instructions previously executed by the microprocessor. The predicting unit accumulates the prediction history and uses the prediction history to make predictions related to subsequent instruction executions. The storage comprises a plurality of portions separately controllable for accumulating the prediction history. The microprocessor also includes a control unit that detects the microprocessor is running an operating system routine and controls the predicting unit to use only a fraction of the plurality of portions of the storage to accumulate the prediction history while the microprocessor is running the operating system routine.

公开(公告)号：EP2997478A1

公开(公告)日：2016-03-23

申请号：EP14891591.1

申请日：2014-11-26

申请人： VIA Alliance Semiconductor Co., Ltd.

发明人： PARKS, Terry ,  EDDY, Colin ,  MOHAN, Viswanath ,  BUNDA, John, D.

IPC分类号： G06F12/10

CPC分类号： G06F12/0891 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/1063 ,  G06F12/109 ,  G06F15/7839 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/683

摘要： A processor includes translation-lookaside buffer (TLB) and a mapping module. The TLB includes a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address translation and a valid bit vector, wherein each bit of the valid bit vector indicates, for a respective address translation context, the address translation is valid if set and invalid if clear. The TLB also includes an invalidation bit vector having bits corresponding to the bits of the valid bit vector of the plurality of entries, wherein a set bit of the invalidation bit vector indicates to simultaneously clear the corresponding bit of the valid bit vector of each entry of the plurality of entries. The mapping module generates the invalidation bit vector.

公开(公告)号：EP2972797A1

公开(公告)日：2016-01-20

申请号：EP14880052.7

申请日：2014-12-12

申请人： VIA Alliance Semiconductor Co., Ltd.

发明人： HOOKER, Rodney, E. ,  PARKS, Terry ,  BUNDA, John, D.

IPC分类号： G06F9/38

CPC分类号： G06F9/46 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3844 ,  G06F9/3851 ,  G06F9/4403

摘要： A microprocessor includes a predicting unit having storage for holding a prediction history of characteristics of instructions previously executed by the microprocessor. The predicting unit accumulates the prediction history and uses the prediction history to make predictions related to subsequent instruction executions. The storage comprises a plurality of portions separately controllable for accumulating the prediction history. The microprocessor also includes a control unit that detects the microprocessor is running an operating system routine and controls the predicting unit to use only a fraction of the plurality of portions of the storage to accumulate the prediction history while the microprocessor is running the operating system routine.