公开(公告)号：EP3219043B1

公开(公告)日：2018-12-12

申请号：EP15795111.2

申请日：2015-10-30

Applicant: Giesecke+Devrient Mobile Security GmbH

Inventor： DREXLER, Hermann ,  BAUER, Sven ,  PULKUS, Jürgen

IPC: H04L9/00 ,  H04L9/06

CPC classification number: G09C1/06 ,  G06F9/4403 ,  G06F21/12 ,  G09C1/00 ,  H04L9/002 ,  H04L9/0618 ,  H04L9/0625 ,  H04L9/0631 ,  H04L9/0822 ,  H04L2209/043 ,  H04L2209/08 ,  H04L2209/16

公开(公告)号：EP3388937A1

公开(公告)日：2018-10-17

申请号：EP17207681.2

申请日：2017-12-15

Applicant: Quanta Computer Inc.

Inventor： Shih, Ching-Chih

IPC: G06F9/4401 ,  H04L12/24

CPC classification number: G06F12/126 ,  G06F9/4401 ,  G06F9/4403 ,  G06F2212/1044 ,  H04L41/0672 ,  H04L41/0813

Abstract: A network system is directed to the efficient management of computer resources, including removal of unused objects within a network system. The network system includes a plurality of processing nodes, where each processing node includes physical storage and a compute node. The compute node is configured to perform operations including receiving a signal to reboot in erase mode, reconfiguring, by a management controller associated with the compute node, the compute node to boot up in the erase mode; and rebooting in erase mode and performing an erase of the at least one processing node.

公开(公告)号：EP2643576B1

公开(公告)日：2018-09-12

申请号：EP10860036.2

申请日：2010-11-22

Applicant: NXP USA, Inc.

Inventor： MAIOLANI, Mark ,  ROBERTSON, Alistair

IPC: G06F9/4401 ,  F02D41/06 ,  F02D41/24 ,  F02D41/26

CPC classification number: G06F9/4401 ,  F02D41/064 ,  F02D41/2432 ,  F02D41/2487 ,  F02D41/266 ,  G06F9/4403

Abstract: A method for enabling calibration during start-up of a micro controller unit device is provided. The method comprises, within the MCU device, reading overlay initialization data from at least one memory element within an external support device operably coupled to the MCU device, and configuring memory mapping functionality of the MCU device to overlay data stored within at least a part of device memory of the MCU device with calibration data stored within the at least one memory element of the external support device in accordance with the overlay initialization data.

公开(公告)号：EP2251781B1

公开(公告)日：2018-08-15

申请号：EP10250646.6

申请日：2010-03-30

Applicant: Intel Corporation

Inventor： Van de Ven, Adriaan

IPC: G06F9/4401 ,  G06F3/06 ,  G06F12/0862 ,  G06F9/445

CPC classification number: G06F9/4406 ,  G06F3/0611 ,  G06F3/0643 ,  G06F3/0647 ,  G06F3/0685 ,  G06F9/4403 ,  G06F9/4408 ,  G06F9/44505 ,  G06F9/44578 ,  G06F12/0862 ,  G06F2212/602 ,  G06F2212/6026

Abstract: In one embodiment, the present invention includes a method for generating a list of files accessed during an operating system (OS) boot process to profile the OS boot process, and optimizing the list of files to generate an optimized file list for use in future OS boot processes, where the optimizing is according to a first optimization technique if the files were accessed from a solid state medium and according to a second optimization technique if the files were accessed from a rotating medium. Other embodiments are described and claimed.

公开(公告)号：EP3335095A4

公开(公告)日：2018-07-25

申请号：EP16835323

申请日：2016-07-18

Applicant: SAMSUNG ELECTRONICS CO LTD

Inventor： JUNG IN-HYUNG ,  LEE CHANG-GUE ,  HYEON TAEJIN ,  KIM HYUNSOO ,  KIM MINHO ,  BAEK JONG-WU

IPC: G06F3/01 ,  G06F9/44

CPC classification number: G06F9/4403 ,  G06F9/4405

Abstract: An electronic device is provided such that a user can experience a quick launch of an application therein. The electronic device includes a housing, a display, an input unit, a processor, a non-volatile memory to store an application program, and a volatile memory to store instructions that allow the processor to load a first part of the application program in the volatile memory based on a first change of state of the electronic device, to load a second part of the application program in the volatile memory based on a second change of state of the electronic device and to display an image or text generated by the loaded first or second part. Since at least part of the application is preloaded before the second input is generated, only the remainder of the application has to be loaded in order to execute the application after the second input is generated.

公开(公告)号：EP3201763A4

公开(公告)日：2018-07-11

申请号：EP15880418

申请日：2015-01-29

Applicant: HEWLETT PACKARD DEVELOPMENT CO

Inventor： COSTA CARLOS HAAS ,  PEREZ TACIANO DRECKMANN ,  PERONE CHRISTIAN ,  SILVA THIAGO ,  WALRATH CRAIG A

IPC: G06F9/44 ,  G06F1/32 ,  G06F9/4401 ,  G06F9/455 ,  G06F11/14 ,  G06F12/00 ,  G06F21/57

CPC classification number: G06F1/3206 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/325 ,  G06F9/4403 ,  G06F9/4418 ,  G06F11/1417 ,  G06F11/1438 ,  G06F12/00 ,  G06F13/42 ,  G06F21/575 ,  G06F2009/45575 ,  H04L49/15

Abstract: As part of starting a system including a system-on-a-chip (SoC) device fro a mode in which power is removed from the system, the SoC device determines, based on the metadata, whether to resume the system to a prior system state. In response to the metadata indicating that the system is to be resumed to the prior system state, the system is resumed to the prior system state using system state information stored in the on-chip non-volatile memory.

公开(公告)号：EP3335095A1

公开(公告)日：2018-06-20

申请号：EP16835323.3

申请日：2016-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNG, In-Hyung ,  LEE, Chang-Gue ,  HYEON, Taejin ,  KIM, Hyunsoo ,  KIM, Minho ,  BAEK, Jong-Wu

IPC: G06F3/01 ,  G06F9/44

CPC classification number: G06F9/4403 ,  G06F9/4405

Abstract: An electronic device is provided such that a user can experience a quick launch of an application therein. The electronic device includes a housing, a display, an input unit, a processor, a non-volatile memory to store an application program, and a volatile memory to store instructions that allow the processor to load a first part of the application program in the volatile memory based on a first change of state of the electronic device, to load a second part of the application program in the volatile memory based on a second change of state of the electronic device and to display an image or text generated by the loaded first or second part. Since at least part of the application is preloaded before the second input is generated, only the remainder of the application has to be loaded in order to execute the application after the second input is generated.

公开(公告)号：EP3299958A1

公开(公告)日：2018-03-28

申请号：EP17200357.6

申请日：2007-04-10

Applicant: Apple Inc.

Inventor： WU, Stephen

IPC: G06F9/445

CPC classification number: G06F9/4406 ,  G06F1/24 ,  G06F9/4401 ,  G06F9/4403 ,  G06F9/44573 ,  G06F12/0246 ,  G06F2212/7201

Abstract: A method for booting a computing device, the method comprising: detecting a reset signal by a non-volatile memory die that includes an internal controller, a register, and a non-volatile memory, wherein the non-volatile memory includes a plurality of pages of data; retrieving, by the internal controller, a predetermined page of data from the non-volatile memory responsive to detecting the reset signal, wherein each of the plurality of pages of data is retrieved from the non-volatile memory as a unit and the predetermined page of data includes at least one instruction for booting the computing device; storing, by the internal controller, the predetermined page of data into the register; fetching, by a host processor, the at least one instruction from the register using at least one simple read command, wherein the simple read command includes an address for randomly accessing locations within the predetermined page of data; executing the at least one instruction by the host processor; and fetching, by the host processor, a second page of data from the non-volatile memory using a read command, wherein the read command retrieves the second page of data, and wherein the second page of data is different from the predetermined page of data.

Abstract translation: 1。一种用于引导计算设备的方法，所述方法包括：通过非易失性存储器裸片检测复位信号，所述非易失性存储器裸片包括内部控制器，寄存器和非易失性存储器，其中所述非易失性存储器包括多个页面 数据的; 由所述内部控制器响应于检测到所述重置信号而从所述非易失性存储器中检索预定页面的数据，其中，所述多个数据页面中的每个页面作为一个单元从所述非易失性存储器中检索，并且所述预定页面 数据包括用于引导计算设备的至少一个指令; 由所述内部控制器将所述预定页数据存储到所述寄存器中; 由主处理器使用至少一个简单读取命令从寄存器取得至少一个指令，其中简单读取命令包括用于随机存取预定数据页面内的位置的地址; 由主处理器执行该至少一个指令; 以及由所述主机处理器使用读取命令从所述非易失性存储器获取第二页数据，其中所述读取命令检索所述第二页数据，并且其中所述第二页数据与所述预定数据页不同 。

公开(公告)号：EP2989636A4

公开(公告)日：2018-03-14

申请号：EP14891593

申请日：2014-12-12

Applicant: VIA ALLIANCE SEMICONDUCTOR CO LTD

Inventor： GLENN HENRY G ,  JAIN DINESH K ,  GASKINS STEPHAN

IPC: G06F9/44 ,  G06F15/177 ,  G11C29/02 ,  H01L27/02

CPC classification number: G06F12/0893 ,  G06F1/3275 ,  G06F8/66 ,  G06F9/4403 ,  G06F12/0811 ,  G06F12/12 ,  G06F15/177 ,  G06F2212/222 ,  G06F2212/283 ,  G06F2212/601 ,  G11C7/20 ,  G11C17/16 ,  G11C17/18 ,  G11C2029/4402

Abstract: An apparatus includes a fuse array and a plurality of cores. The fuse array is programmed with compressed data. Each of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed data, and to store decompressed data sets for one or more cache memories within the each of the plurality of cores in a stores that is coupled to the each of the plurality of cores. Each of the plurality of cores has reset logic and sleep logic. The reset logic employs the decompressed data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed data sets to initialize the one or more caches following the power gating event.

公开(公告)号：EP2989553A4

公开(公告)日：2018-03-14

申请号：EP14891596

申请日：2014-12-12

Applicant: VIA ALLIANCE SEMICONDUCTOR CO LTD

Inventor： HENRY G GLENN ,  JAIN DINESH K ,  GASKINS STEPHAN

IPC: G06F9/44 ,  G06F15/177 ,  G11C29/02 ,  H01L27/02

CPC classification number: G06F12/0893 ,  G06F1/3275 ,  G06F8/66 ,  G06F9/4403 ,  G06F12/0811 ,  G06F12/12 ,  G06F15/177 ,  G06F2212/222 ,  G06F2212/283 ,  G06F2212/601 ,  G11C7/20 ,  G11C17/16 ,  G11C17/18 ,  G11C2029/4402

Abstract: An apparatus includes a fuse array and a plurality of cores. The fuse array is programmed with compressed data. Each of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed data, and to store decompressed data sets for one or more cache memories within the each of the plurality of cores in a stores that is coupled to the each of the plurality of cores. Each of the plurality of cores has reset logic and sleep logic. The reset logic employs the decompressed data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed data sets to initialize the one or more caches following the power gating event.