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公开(公告)号:EP1307820A4
公开(公告)日:2007-05-02
申请号:EP01942239
申请日:2001-06-06
IPC分类号: H04Q3/52 , G02B6/35 , G06F13/40 , H01L23/02 , H01L23/48 , H01L23/538 , H04L12/56 , H04Q1/00 , G06F13/38
CPC分类号: H01L23/5382 , G06F13/4022 , H01L2224/16225 , H01L2924/15311 , H01L2924/3011 , H04L49/101 , H04L49/65
摘要: A crosspoint switch including a switch matrix modules (101) and programming features (109). A switch matrix modules include input lines tied to inputs of the switch through recompensation networks (201, 203). The programming features include user initialization states and reduced and grouping command configuration operations.
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公开(公告)号:EP1023793A4
公开(公告)日:2005-08-03
申请号:EP99943914
申请日:1999-08-25
CPC分类号: H04L25/063 , H04L7/0037 , H04L7/033 , H04L7/0334
摘要: A microprocessor (45) controlled data recovery unit with an adjustable sampling and signal comparison level. The data recovery unit includes a data channel (47a) and a monitor channel (47b). The monitor channel samples an incoming data stream in a varying manner. The results of the sampling in the monitor channel are used to adjust the sampling and comparing of the signal in the data channel. The data recovery unit includes a PLL (35) based clock recovery unit in one embodiment, and in another embodiment the clock signal is derived by the microprocessor.
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