摘要:
A time-to-digital converter (110) comprising at least one chain of delay elements (126.1,..., 126.N), wherein a status of said chain of delay elements (126.1,..., 126.N) represents a digital signal relating to a time interval to be converted, wherein said time- to-digital converter (110) comprises means (156) for providing trigger signals (154) having statistically equally distributed variable positions relative to a pulse forwarded in said chain of delay elements (126.1,..., 126.N), means (130) for capturing said status of said chain of delay elements (126.1,..., 126.N) in response to said calibration trigger signals (154), wherein said status depends on delay times of said delay elements (126.1,..., 126.N), means for determining an actual contribution of at least some of said delay elements (126.1,..., 126.N) to an overall delay of said chain of delay elements (126.1,..., 126.N) on the basis of occurrences of pulse positions in response to said calibration trigger signals (154), and means (164) for taking into account said actual contribution of at least some of said delay elements (126.1,..., 126.N) when converting said time interval into said digital signal (168).
摘要:
A device (203) for processing test data, the device (203) comprising a data input interface (204) adapted for receiving primary test data indicative of a test carried out for testing a device under test (202), the primary test data being provided in a primary format, a processing unit (205) adapted for generating secondary test data in a secondary format by transforming, by carrying out a coordinate transformation, the primary test data from the primary format into the secondary format, and a data output interface (206) adapted for providing the secondary test data in the secondary format for storing the secondary test data in a plurality of storage units (207a to 207c).
摘要:
A time-to-digital converter (110) comprising at least one chain of delay elements (126.1,..., 126.N), wherein a status of said chain of delay elements (126.1,..., 126.N) represents a digital signal relating to a time interval to be converted, wherein said time- to-digital converter (110) comprises means (156) for providing trigger signals (154) having statistically equally distributed variable positions relative to a pulse forwarded in said chain of delay elements (126.1,..., 126.N), means (130) for capturing said status of said chain of delay elements (126.1,..., 126.N) in response to said calibration trigger signals (154), wherein said status depends on delay times of said delay elements (126.1,..., 126.N), means for determining an actual contribution of at least some of said delay elements (126.1,..., 126.N) to an overall delay of said chain of delay elements (126.1,..., 126.N) on the basis of occurrences of pulse positions in response to said calibration trigger signals (154), and means (164) for taking into account said actual contribution of at least some of said delay elements (126.1,..., 126.N) when converting said time interval into said digital signal (168).
摘要:
A signal processing device (100), preferably an undersampling ADC using coherent sampling, is presented for processing a signal (102) , the signal processing device (100) comprising a comparator unit (105) for comparing the signal (102) with a reference signal (106), a generation unit (105, 130) for generating digital result signals (110) indicative of the result of the comparing, an evaluation unit (112) for determining transition times of the digital result signals (110), and an output signal calculation unit (115) adapted for calculating essentially uniformly spaced output signals (116).
摘要:
An asynchronous sigma delta digital to analog converter (100) for converting a digital input signal (u[k]) into an analog output signal (f(t)), the digital to analog converter (100) comprising an asynchronous sigma delta modulator (120) comprising a low pass filter (104) and a comparator (106) and being supplied with the digital input signal (u[k]), and a clock sample unit (108) adapted to sample a signal (x(t)) processed by the comparator (106) based on a clock signal (fb), thereby generating the analog output signal (f(t)).
摘要:
A signal processing device (100) for processing a repetitive signal (102), the signal processing device (100) comprising a determining unit (103) for determining a number of points of time for undersampling the repetitive signal (102), a comparator unit (105) for comparing, at the number of points of time, the repetitive signal (102) with a reference signal (106), a generation unit (105) for generating digital result signals (110) indicative of the result of the comparing, and an evaluation unit (112) for determining transition times of the digital result signals (110).
摘要:
A device (203) for processing test data, the device (203) comprising a data input interface (204) adapted for receiving primary test data indicative of a test carried out for testing a device under test (202), the primary test data being provided in a primary format, a processing unit (205) adapted for generating secondary test data in a secondary format by transforming, by carrying out a coordinate transformation, the primary test data from the primary format into the secondary format, and a data output interface (206) adapted for providing the secondary test data in the secondary format for storing the secondary test data in a plurality of storage units (207a to 207c).
摘要:
A signal processing device (100) comprising an adjustment unit (103) for adjusting a time duration of each of a plurality of signals (101, 110) individually in accordance with an amplitude of the respective signal (101, 110) to thereby generate calibrated signals (104, 111), and a combining unit (120) for combining the calibrated signals (104, 111).