公开(公告)号：EP0688451A1

公开(公告)日：1995-12-27

申请号：EP94910853.0

申请日：1994-03-11

申请人： Xilinx, Inc.

发明人： BUCH, Kiran, B. ,  LAW, Edwin, S. ,  CHU, Jakong, J.

IPC分类号： G06F11 ,  G01R31 ,  G06F17 ,  H01L21

CPC分类号： G01R31/318519 ,  G06F11/261 ,  G06F17/5068 ,  Y10S706/921

摘要： Method and apparatus for producing mask-configured integrated circuits which are pin, logic, and timing compatible substitutes for user-configured logic arrays (10), without the need for logic or timing simulations of the mask-configured circuit design. Scan testing networks of test blocks and modified flip-flops are included in the mask-configured substitutes to test functionality. Logic compatibility to the user-configured logic array (an FPGA) (10) is preserved by clustering together in the mask-configured integrated circuit (a gate array) (16) all of the logic gates which perform the functions of a particular FPGA logic block. Moreover, only those FPGA logic gates or functions which are used are replicated in the gate array, to conserve chip area.