公开(公告)号：EP0771071A1

公开(公告)日：1997-05-02

申请号：EP96116954.7

申请日：1996-10-22

申请人： YOZAN INC. ,  NTT MOBILE COMMUNICATIONS NETWORK INC.

发明人： Shou, Guoliang c/o Yozan Inc. ,  Zhou, Changming c/o Yozan Inc. ,  Yamamoto, Makoto c/o Yozan Inc. ,  Takatori, Sunao c/o Yozan Inc. ,  Adachi, Fumiyuki ,  Sawahashi, Mamoru

IPC分类号： H03H11/04 ,  H03H17/02

CPC分类号： H03H11/04 ,  H03H17/0254

摘要： A matched filter circuit with a sampling and holding circuits which are classified into two groups. A control circuit successively closes one of switches in the first group every chip time, at the same time, closes one of switches in the second group at a shifted timing by 1/2 chip time from the timing of the first group.

摘要翻译： 带有采样和保持电路的匹配滤波器电路，分为两组。 控制电路在每个码片时间连续地闭合第一组中的一个开关，同时，在从第一组的定时开始的移位时间1/2码片时间处闭合第二组中的一个开关。

公开(公告)号：EP0771071B1

公开(公告)日：2001-08-16

申请号：EP96116954.7

申请日：1996-10-22

申请人： Yozan Inc. ,  NTT MOBILE COMMUNICATIONS NETWORK INC.

发明人： Shou, Guoliang c/o Yozan Inc. ,  Zhou, Changming c/o Yozan Inc. ,  Yamamoto, Makoto c/o Yozan Inc. ,  Takatori, Sunao c/o Yozan Inc. ,  Adachi, Fumiyuki ,  Sawahashi, Mamoru

IPC分类号： H03H11/04 ,  H03H17/02

CPC分类号： H03H11/04 ,  H03H17/0254

公开(公告)号：EP0585861A3

公开(公告)日：1994-12-14

申请号：EP93113849.9

申请日：1993-08-30

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang, c/o Yozan Inc. ,  Takatori,Sunao, c/o Yozan Inc. ,  Yamamoto, Makoto c/o Yozan Inc.

IPC分类号： G06K9/64

CPC分类号： G06K9/6203

摘要： A plurality of successive pixels of a template and corresponding pixels of an input image inputted into a hardware with a function of multiplication, addition and subtraction. A summation of differences is calculated by the hardware between the corresponding pixels of template and input image, and written into a work memory. An image verification is performed by integrating successive results of the summation for the total area to be verified in high speed with utilizing a general purpose image processing hardware, without using a special purpose image processing hardware.

公开(公告)号：EP0779705A2

公开(公告)日：1997-06-18

申请号：EP96119554.2

申请日：1996-12-05

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Zhou, Changmingc/o Yozan Inc. ,  Shou, Guoliang c/o Yozan Inc. ,  Yamamoto, Makoto c/o Yozan Inc. ,  Takatori, Sunao c/o Yozan Inc.

IPC分类号： H03F1/34 ,  H03F3/345

CPC分类号： H03F3/72

摘要： The present invention has an object to provide an inverted amplifying circuit with improved accuracy of output and reduced electric power consumption. In an inverted amplifying circuit according to the present invention, a MOS switch is connected between pMOS and nMOS of a CMOS inverter and between balancing resistances. The MOS switch is opened when the inverted amplifying circuit does not work.

公开(公告)号：EP0782288A2

公开(公告)日：1997-07-02

申请号：EP96120802.2

申请日：1996-12-23

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang c/o Yozan Inc. ,  Zhou, Changming c/o Yozan Inc. ,  Zhou, Xuping c/o Yozan Inc. ,  Yamamoto, Makoto c/o Yozan Inc. ,  Takatori, Sunao c/o Yozan Inc.

IPC分类号： H04J13/00

CPC分类号： H04J13/0022 ,  H04J13/10 ,  H04J2013/0037

摘要： The present invention has an object to provide a spread spectrum communication system for heightening the speed of communication. The present invention transfers the first PN code sequence itself as the first component, adds and transfer zero or more PN code sequences of the second PN code sequence given a phase difference as the second component, and defines an information for transmitting by the number of the second PN codes corresponding to a cycle of said first PN code sequence.

摘要翻译： 本发明的一个目的是提供一种用于提高通信速度的扩频通信系统。 本发明将第一PN码序列本身作为第一分量进行传送，将给定相位差的第二PN码序列的零个或多个PN码序列作为第二分量相加和传送，并且将用于发送的信息 第二PN码对应于所述第一PN码序列的周期。

公开(公告)号：EP0585861A2

公开(公告)日：1994-03-09

申请号：EP93113849.9

申请日：1993-08-30

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang, c/o Yozan Inc. ,  Takatori,Sunao, c/o Yozan Inc. ,  Yamamoto, Makoto c/o Yozan Inc.

IPC分类号： G06K9/64

CPC分类号： G06K9/6203

摘要： A plurality of successive pixels of a template and corresponding pixels of an input image inputted into a hardware with a function of multiplication, addition and subtraction. A summation of differences is calculated by the hardware between the corresponding pixels of template and input image, and written into a work memory. An image verification is performed by integrating successive results of the summation for the total area to be verified in high speed with utilizing a general purpose image processing hardware, without using a special purpose image processing hardware.

摘要翻译： 模板的多个连续像素和输入图像的相应像素输入到具有乘法，加法和减法功能的硬件中。 通过模板和输入图像的相应像素之间的硬件来计算差值的总和，并将其写入工作存储器中。 不使用专用图像处理硬件，而是利用通用图像处理硬件，通过对要验证的总区域的总和的连续结果进行集成来执行图像验证。