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19 条记录 (耗时 0.009 秒)

    Interface circuit
    1.
    发明公开
    Interface circuit 失效
    Schnittstellenschaltung

    公开(公告)号：EP0707276A1

    公开(公告)日：1996-04-17

    申请号：EP95115334.5

    申请日：1995-09-28

    申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

    发明人： Shou, Guoliang, c/o Yozan Inc. ,  Motohashi, Kazunori, c/o Yozan Inc. ,  Yamamoto, Makoto, c/o Yozan Inc. ,  Takatori, Sunao, c/o Yozan Inc.

    IPC分类号： G06J1/00

    CPC分类号： G06J1/00

    摘要： An interface circuit comprising a digital to analog converter which comprises a register for receiving and holding each bit of a digital signal, a capacitive coupling for integrating total bits held in the register with weighting, an inverted amplifier circuit for receiving an output of the capacitive coupling and for outputting an analog output voltage, and a feedback capacitance for connecting an outputs of the inverted amplifier circuit to an input of the inverted amplifier circuit, an analog signal line to which the analog output voltage is connected, and an analog to digital converter which comprises a plurality thresholding circuits with stepwise thresholds to which the analog signal line is commonly inputted, each the thresholding circuit receiving outputs of the thresholding circuits of higher threshold with weighting so that the thresholding circuits repeatedly change the outputs from high level to low level or from low level to high level.

    摘要翻译： 一种接口电路，包括数模转换器，其包括用于接收和保持数字信号的每一位的寄存器，用于将保持在寄存器中的总比特积分为加权的电容耦合，用于接收电容耦合的输出的反相放大器电路 并且用于输出模拟输出电压，以及用于将反相放大器电路的输出连接到反相放大器电路的输入的反馈电容，连接有模拟输出电压的模拟信号线以及模数转换器， 包括具有逐步阈值的多个阈值电路，模拟信号线被共同输入，每个阈值电路接收具有加权的较高阈值的阈值电路的输出，使得阈值电路重复地将输出从高电平改变为低电平或从 低水平到高水平。

    Multiplication circuit
    2.
    发明公开
    Multiplication circuit 失效
    乘法电路

    公开(公告)号：EP0707275A1

    公开(公告)日：1996-04-17

    申请号：EP95115333.7

    申请日：1995-09-28

    申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

    发明人： Shou, Guoliang, c/o Yozan Inc. ,  Motohashi, Kazunori, c/o Yozan Inc. ,  Yamamoto, Makoto, c/o Yozan Inc. ,  Takatori, Sunao, c/o Yozan Inc.

    IPC分类号： G06J1/00

    CPC分类号： G06J1/00

    摘要： A multiplication circuit comprises a plurality of the first switching means for receiving a common analog input voltage and a reference voltage and for alternatively outputting the input voltage or the reference voltage, the first capacitive coupling with a plurality of capacitances for receiving outputs of the first switching means are inputted, the first inverted amplifier for receiving an output of the first capasitive coupling, an output of the first inverted amplifier being fed back to its input; the second inverted amplifier for receiving the output of the first inverted amplifier, an output of the second inverted amplifier being fed back to its inputand characterized in that one or more of the capacitances in the first capacitive coupling is connected to the second capacitive coupling with a plurality of capacitances and that a plurality of the second switching means are connected to each capacitances of the second capacitive coupling, the second switching means alternatively outputting the analog input voltage or the reference voltage.

    摘要翻译： 乘法电路包括多个第一开关装置，用于接收公共模拟输入电压和参考电压，并用于交替输出输入电压或参考电压，第一电容耦合具有多​​个电容，用于接收第一开关的输出 装置被输入，第一反相放大器用于接收第一无感耦合的输出，第一反相放大器的输出被反馈到其输入端; 所述第二反相放大器用于接收所述第一反相放大器的输出，所述第二反相放大器的输出被反馈到其输入端，并且其特征在于，所述第一电容耦合中的一个或多个电容连接到所述第二电容耦合， 多个电容并且多个第二开关装置连接到第二电容耦合的每个电容，第二开关装置可选地输出模拟输入电压或参考电压。

    Capacitance forming method
    3.
    发明公开
    Capacitance forming method 失效
    Kapazitätserzeugungsverfahren

    公开(公告)号：EP0704904A1

    公开(公告)日：1996-04-03

    申请号：EP95115448.3

    申请日：1995-09-29

    申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

    发明人： Shou, Guoliang, c/o Yozan Inc. ,  Motohashi, Kazunori, c/o Yozan Inc. ,  Yamahoto, Makoto, c/o Yozan Inc. ,  Takatori, Sunao, c/o Yozan Inc.

    IPC分类号： H01L27/08 ,  H01L27/10

    CPC分类号： H01L27/0805 ,  H01L27/101

    摘要： A capacitance forming method for forming capacitances corresponding to a plurality of constant numbers within a large scale integrated circuit (LSI) comprises steps of defining a unit capacitance with a predetermined shape, defining an arrangement of a plurality of the unit capacitances of a number necessary for total capacity of capacitances to be formed in two dimension in an area of the LSI, selecting the unit capacitances of a number corresponding to the maximal capacity among capacities of the capacitances to be formed so that the selected unit capacitances are equivalently dispersed over the area, and successively selecting other of the capacitances than the capacitance of the maximal capacity in the order of capacities, and selecting the unit capacitances of a number corresponding to a capacity of each the capacitance selected so that the selected unit capacitances are equivalently dispersed over an area of the rest of the unit capacitances which have not selected yet.

    摘要翻译： 用于在大规模集成电路（LSI）内形成对应于多个常数的电容的电容形成方法包括以预定形状定义单位电容的步骤，限定多个单位电容的排列， 在LSI的区域中形成二维电容的总容量，选择与要形成的电容的容量之间的最大容量对应的数字的单位电容，使得所选择的单位电容等效地分散在该区域上， 并且依次选择容量级别中最大容量的电容以外的其他电容，并且选择与所选择的每个电容的容量对应的数量的单位电容，使得所选择的单位电容等价地分散在 剩余的单位电容尚未选择。

    Lock with an authenticated open and set function, and IC card for the same
    5.
    发明公开
    Lock with an authenticated open and set function, and IC card for the same 审中-公开
    Schloss mit authentifizierterÖffnungs-und Setzfunktion和IC-Kartedafür

    公开(公告)号：EP1128008A2

    公开(公告)日：2001-08-29

    申请号：EP01104135.7

    申请日：2001-02-21

    申请人： Yozan Inc.

    发明人： Takatori, Sunao, c/o Yozan Inc. ,  Kiyomatsu, Hisanori, c/o Yozan Inc.

    IPC分类号： E05B49/00

    CPC分类号： G07C9/00309 ,  G07C2009/00373 ,  G07C2009/00769 ,  G07C2209/08

    摘要： The present invention provides a lock with an authenticated open and set function, by which the lock may be opened without any bothersome operation for inserting a key to open the lock. An IC card 3 sends user identification information stored in a memory 34 to an authenticated open and set function unit 1. The authenticated open and set function unit 1 sends the user identification information to a collator 15 under the control of a controller 11 on reception of it. The collator 15 collates the user identification information sent from the IC card 3 with that stored in a memory 16. When both of the user identification information are coincided with each other, the collator 15 sends the collation signal, which is indicative of the user being authenticated, to the controller 11. The controller 11 gives a controller 17 a command to open a lock installed in a door 2. The controller 17 opens the lock based on the command by the controller 11.

    摘要翻译： 本发明提供了一种具有认证的打开和设定功能的锁，通过该锁可以打开锁，而无需任何麻烦的操作来插入钥匙来打开锁。 IC卡3将存储在存储器34中的用户识别信息发送给认证的打开和设定功能单元1.认证的打开和设定功能单元1在接收到控制器11的控制下将用户识别信息发送到整理器15 它。 整理机15将从IC卡3发送的用户识别信息与存储在存储器16中的用户识别信息进行核对。当两个用户识别信息彼此一致时，整理器15发送对照信号，该对照信号指示用户为 控制器11给控制器17打开安装在门2中的锁的命令。控制器17基于控制器11的命令来打开锁。

    Complex number calculation circuit
    7.
    发明公开
    Complex number calculation circuit 失效
    电路，用于计算复数

    公开(公告)号：EP0986019A2

    公开(公告)日：2000-03-15

    申请号：EP99123783.5

    申请日：1996-09-19

    申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

    发明人： Zhou, Changming, c/o Yozan Inc. ,  Shou, Guoliang, c/o Yozan Inc. ,  Yamamoto, Makoto, c/o Yozan Inc. ,  Takatori, Sunao, c/o Yozan Inc.

    IPC分类号： G06G7/22

    CPC分类号： G06G7/22 ,  G06J1/00

    摘要： A complex number calculation circuit for directly multiplying a complex number of an analog signal by a digital complex number as a multiplier. A capacitive coupling is used with a plurality of parallel capacitances corresponding to weights of bits of real and imaginary parts of the multiplier. Sign of the multiplier is represented by selection of outputs paths. A complex number calculation circuit for calculating approximated absolute value suitable for an analog architecture. Inverter circuits are used for linear inversion of analog values, and capacitive couplings are use for weighted addition. Analog maximum and minimum circuits with parallel MOSs are used for maximum and minimum calculation.

    A/D Converter
    9.
    发明公开
    A/D Converter 失效
    A / D转换器

    公开(公告)号：EP0704979A1

    公开(公告)日：1996-04-03

    申请号：EP95114829.5

    申请日：1995-09-20

    申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

    发明人： Shou, Guoliang, c/o Yozan Inc. ,  Motohashi, Kazunori, c/o Yozan Inc. ,  Yamamoto, Makoto, c/o Yozan Inc. ,  Takatori, Sunao, c/o Yozan Inc.

    IPC分类号： H03M1/14 ,  H03M1/36

    CPC分类号： H03M1/145 ,  H03M1/804

    摘要： An A/D converter comprises of the first inverter having a linear characteristic and receiving an analog input voltage, the first quantizing circuit for outputting a quantized output of the analog input voltage, a capacitive coupling to which an output of the first inverter and the first quantizing circuit are inputted, the second inverter receiving an output of the capacitive coupling and having the same characteristic of the first inverter, and the second quantizing circuit receiving an output of the second inverter and quantizing an output of the second inverter.

    摘要翻译： A / D转换器包括具有线性特性并接收模拟输入电压的第一反相器，第一量化电路用于输出模拟输入电压的量化输出，电容耦合，第一反相器的输出和第一反相器 量化电路被输入，第二反相器接收电容耦合的输出并具有与第一反相器相同的特性，第二量化电路接收第二反相器的输出并量化第二反相器的输出。