摘要:
A plurality of sets of spreading code sequences are store in registers and selectively supplied to matched filters. The soft-handover, multi-code processing and long-delay paths can be processed by a small circuits.
摘要:
A signal reception apparatus in the spectrum spread communication system requires only a small amount of circuitry and consumes a small amount of electric power. A quadrature detector decomposes received signals into in-phase components and quadrature components, and supplies them to a complex-type matched filter. The complex-type matched filter de-spreads the in-phase components and the quadrature components and sends them to a multi-path selector. The multi-path selector selects, from among the received de-spread signals, multiple paths having high levels of signal electric powers and sends the received signals of the selected paths to multiple phase correction blocks. Analog operation circuits 31 through 34 calculate phase errors of the received signals of two successive pilot symbol blocks for each path. An analog operation circuit 40 corrects the phases of the received signals of the information symbol block that has been received between the two successive pilot symbol blocks. A RAKE combiner synchronously combines the phase-corrected de-spread received signals of each path.
摘要:
A signal reception apparatus for DS-CDMA communication system having a complex matched filter for despreading a received signal into I-and Q-components D i and D q of despread signal. D i and D q are input to a path selection portion 13 for extracting a phase error in a pilot symbol block of the despread signal. A phase compensation signal is calculated according to the phase error in the portion 13. An information symbol is compensated according to the phase compensation signal. An electrical power is calculated from an average of the phase compensation signal of several slots for selecting paths to be received. The selected paths are combined with phase synchronized by a rake combiner 14.
摘要:
The present invention realizes a rapid and efficient cell search and small-size instrument for an asynchronous DS-CDMA cellular system. This cell search detects the correlation between the received signal and the short code of the control channel, and matched filter 22 detects the maximum electric power correlation peak location. Next, using correlators 28-1 to 28-n which are parallelly set in a plurality for RAKE processing with plurality, identifies the long code that is set in the system with the detected long code timing. After the long code is synchronized, a multipath signal is received using 28-1 to 28-n, and the data is judged by RAKE processing. When peripheral cell search is executed, after long code timing is detected by using matched filter 22, the long code of the candidate peripheral cell is designated using the same matched filter. Handover is safely realized by receiving the signal from the connected base station by correlators 28-1 to 28-n, and the base station signal through handover by 22.
摘要:
A (direct-sequence code division multiple access) DS-CDMA cellular system includes a plurality of cells each having one base station and a plurality of mobile stations. A signal transmitted form the base station is distinguished by a long code which is different from the others being uniquely allocated to each cell. A long code synchronization timing being detected by a correlation using a common short code. The long codes are searched in each mobile station by a partial correlation in a timing according to the long code synchronization timing. The partial correlation is a correlation between a signal received and a segment of a code defined by a part of the long code, the part being shifted in the long code. Further, the long codes are classified into a plurality of long code groups defined by long code group identification codes. A delay profile of the long code group identification code is detected and is compensated in fading according to said short code. Then, the long code group identification code is combined by rake combining, and is demodulated.
摘要:
A plurality of sets of spreading code sequences are stored in registers. In case of soft hand-over, multi-code and long-delay paths, it is possible that the correlation peaks derived by the different PN sequences overlap. The spreading code sequences then are shifted by the generator registers in order to separate the peaks by one or more chips.
摘要:
The present invention has an object to provide a filter circuit largely reducing electric power to consume compared with a conventional one, as well as realizing the first acquisition in enough high speed. In a filter circuit according to the present invention, a matched filter and a sliding correlator are used in parallel, the first acquisition and holding is executed by a matched filter, a correlating operation is executed by a sliding correlator and a voltage is stopped to supply to the matched filter.
摘要:
An analog input signal is converted into digital data by an A/D converted, a digital multiplication as a correlation calculation is executed by a plurality of exclusive-OR circuits, and an analog addition of outputs of the exclusive-OR circuits is performed. In the multiplication, the digital data is multiplied a spreading code of one bit. The exclusive-OR outputs are added for each weight of bits, and the addition results are weighted and summed up.
摘要:
A π/n shift PSK demodulator of this invention is formed with a digital logical means through the following method. XOR4 calculates the ex-OR operation between the present sample through π/4 shift QPSK output from SH2 and the previous one output from SH1. Accumulating 1 among the outputs from XOR4 in the first operation means 5 and multiplying it by π/8 obtains the absolute phase difference between the present and the previous symbols. The former or latter four bits from SH1 are subtracted from the corresponding former or latter four bits from SH2, and the result of each bit is summed and its sign is added to the absolute phase data in sign addition means 10. After the phase offset is subtracted from the outputs from 10, it is demodulated into the original one in judgment circuit 13.
摘要:
Phases of the spread spectrum signal are corrected with a high degree of accuracy by a minimum of circuitry. One of phase correction circuits 31 - 34 of the receiver corresponds to each path. The I-component and Q-component of a despread output are supplied to the phase correction circuits 31 - 34. A phase error extractor 1 extracts the first phase error from a received pilot block. A phase corrector 2 corrects the phase error of a received information symbol using a correction vector that has been calculated based on the first phase error. The RAKE synthesizer 25 synthesizes the corrected received signal with outputs of the phase correction circuits of other paths and outputs the synthesized signal to a temporary determiner 3 which temporarily determines an information symbol to be processed. The phase error is modified in a correction vector modifier 4 using the temporary determination result. A new correction vector is calculated based on the modified phase error. In this way, the correction vectors are sequentially modified based on the temporary determination results for the information symbols.