公开(公告)号：EP0424119A2

公开(公告)日：1991-04-24

申请号：EP90311387.6

申请日：1990-10-17

申请人： ZORAN CORPORATION

发明人： Friedlander, Rami ,  Retter, Rafi

IPC分类号： G06F15/332

CPC分类号： G06F17/147 ,  G06T9/007

摘要： A discrete cosine transform/inverse discrete transform or DCT/IDCT integrated circuit capable of performing both DCT and IDCT, includes a processor for processing DCT/IDCT data including, input buffer and arithmetic logic unit for processing incoming data and first pass pre-processed data, multiplier and accumulator unit for performing mathematical operations on DCT/IDCT data, and output buffer and arithmetic logic unit for processing first pass pre-processed data and outgoing data. Also provided is an interleaved random access memory for storing DCT/IDCT data during various stages of processing.

摘要翻译： 离散余弦变换/逆离散变换或能够执行DCT和IDCT的DCT / IDCT的集成电路，包括用于处理DCT / IDCT数据，包括INPUTBUFFER和算术逻辑单元，用于处理输入数据和第一通过预处理的数据的处理器 ，乘法器和累加器单元，用于对DCT / IDCT数据，和输出缓冲器和算术逻辑单元执行数学运算，用于处理第一通过预加工数据和输出数据。 所以被提供给交错随机存取存储器用于在处理的各个阶段中存储DCT / IDCT的数据。

公开(公告)号：EP0262816A2

公开(公告)日：1988-04-06

申请号：EP87307933.9

申请日：1987-09-08

申请人： Zoran Corporation

发明人： Retter, Rafi

IPC分类号： G06F15/332

CPC分类号： G06F17/142

摘要： A pipeline dprocessing computation apparatus for performing the Butterfly operation on complex data (A, B) as weighted by a complex factor (W) in accordance with the equations in which partial products for subsequent data (A 1 , Bi) weighted by a factor (Wi) are obtained while the sum and difference of A and WB are obtained. In a preferred embodiment the total operation for one set of data is eleven clock cycles, and three sets of data can be operated on concurrently whereby two inputs are provided and two outputs obtained every four cycles.

摘要翻译： 一种流水线处理计算装置，用于根据等式X = A + WB Y = A-WB对由复数因子（W）加权的复数数据（A，B）执行蝴蝶操作，其中后续数据的部分积（ A1，B1），得到A和WB的和差。 在一个优选实施例中，一组数据的总操作是11个时钟周期，并且可同时操作三组数据，由此提供两个输入，并且每四个周期获得两个输出。

公开(公告)号：EP0424119A3

公开(公告)日：1992-08-05

申请号：EP90311387.6

申请日：1990-10-17

申请人： ZORAN CORPORATION

发明人： Friedlander, Rami ,  Retter, Rafi

IPC分类号： G06F15/332

CPC分类号： G06F17/147 ,  G06T9/007

摘要： A discrete cosine transform/inverse discrete transform or DCT/IDCT integrated circuit capable of performing both DCT and IDCT, includes a processor for processing DCT/IDCT data including, input buffer and arithmetic logic unit for processing incoming data and first pass pre-processed data, multiplier and accumulator unit for performing mathematical operations on DCT/IDCT data, and output buffer and arithmetic logic unit for processing first pass pre-processed data and outgoing data. Also provided is an interleaved random access memory for storing DCT/IDCT data during various stages of processing.

公开(公告)号：EP0262816A3

公开(公告)日：1991-01-16

申请号：EP87307933.9

申请日：1987-09-08

申请人： Zoran Corporation

发明人： Retter, Rafi

IPC分类号： G06F15/332

CPC分类号： G06F17/142

摘要： A pipeline dprocessing computation apparatus for performing the Butterfly operation on complex data (A, B) as weighted by a complex factor (W) in accordance with the equations in which partial products for subsequent data (A 1 , Bi) weighted by a factor (Wi) are obtained while the sum and difference of A and WB are obtained. In a preferred embodiment the total operation for one set of data is eleven clock cycles, and three sets of data can be operated on concurrently whereby two inputs are provided and two outputs obtained every four cycles.

摘要翻译： 一种流水线处理计算装置，用于根据等式X = A + WB Y = A-WB对由复数因子（W）加权的复数数据（A，B）执行蝴蝶操作，其中后续数据的部分积 A1，B1），得到A和WB的和差。 在一个优选实施例中，一组数据的总操作是11个时钟周期，并且可同时操作三组数据，由此提供两个输入，并且每四个周期获得两个输出。