摘要:
Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.
摘要:
A mobile (cellular) telephone capability is built into a non-mobile appliance, such as a video recorder, television set-top box or personal computer, in order to receive calls from another telephone that is remote of the appliance. The appliance has a unique telephone number that is dialed by the other telephone to establish a direct connection between the two over a mobile telephone network. Data are then sent to the appliance through the network, such as data of pictures taken by a mobile picture telephone and any accompany sound. A user of a picture telephone may conveniently send pictures to his or her home or office while traveling on vacation or business, and even remotely cause such pictures to be sent from the appliance to friends and family.
摘要:
A data processing system and method for performing a wavelet-like transformation (122) and a corresponding inverse wavelet-like transformation (132) is disclosed. The wavelet-like transformation is performed on input data so as to produce decomposed data. For each set of decomposed data samples of the decomposed data, each decomposed data sample of the set is produced by computing a weighted sum of a predefined set of data samples selected from (A) subsets of the set of input data samples, (B) one or more spatially shifted subsets of the set of input data samples, (C) the sets of decomposed data samples, and (D) one or more spatially shifted sets of the sets of decomposed data samples. The weighted sum is computed using only add and bit shift operations. Similarly, the inverse wavelet-like transformation is performed on decomposed data so as to produce reconstructed data (108).
摘要:
A system and method for decoding and displaying a video bitstream representing video images and displaying the video images. The present invention discloses a split memory manager design which is particularly adapted to display UPEG-2 format video images. In addition, the present invention discloses a novel way of managing the video memory used in a video decode and display system. Finally, an intraframe video data compression system and method is disclosed to complement the disclosed video decoding and displaying system.
摘要:
Techniques for modifying data of an image that can be implemented in a digital camera, video image capturing device and other optical systems are provided to correct for image shading variations appearing in data from a two-dimensional photo-sensor. These variations can be caused by imperfect lenses, non-uniform sensitivity across the photo-sensor, and internal reflections within a housing of the optical system, for example. In order to correct for these variations, a small amount of modification data is stored in a small memory within the camera or other optical system, preferably separate correction data for each primary color. The modification data is generated on the fly, at the same rate as the image data is being acquired, so that the modification takes place without slowing down data transfer from the image sensor.
摘要:
A ghost cancellation system for filtering out ghosts in a received video signal including an active filter (14) having a filtering function defined by a first set of coefficients (akold) and having an input and an output. A transmitted ghost cancellation reference (GCR) signal is applied to the input of the active filter during a vertical blanking period to generate a filtered GCR signal at the output of active filter. The filtered GCR signal is compared with a ghostless GCR signal to obtain an error signal, and the filter coefficients are adjusted based on the error signal to obtain a set of new coefficients (aknew). The active filter includes a feedforword FIR filter (14-1) and an adder (14-3) serially connected between the input and the output, a feedback IIR filter (14-2) and a switch (14-4) serially connected between the output and the adder, the feedforward FIR filter and the feedback IIR filter having filtering functions defined by the coefficients.
摘要:
A method of bit rate control and block allocation for discrete cosine transform (DCT) image signal compression includes the steps of (a) partitioning the image signals in blocks (b) calculating DCT coefficients in all blocks, (c) obtaining a measure of block activity (BACT) for each block based on DCT coefficients and for the total image activity (ACT) as a sum of the measures of all block activity, (d) determining a code allocation factor (AF) for each block based on the ratio of block activity (BACT) to target code volume (TCV data) for the coded image date, and (e) allocating bits for each block using the allocation factor (AF) for each block and the target code volume (DCV data). Steps (a-d) are carried out with a first statistical pass through the image data, and step (e) is carried out in a second compression pass through the image data.
摘要:
A discrete cosine transform/inverse discrete transform or DCT/IDCT integrated circuit capable of performing both DCT and IDCT, includes a processor for processing DCT/IDCT data including, input buffer and arithmetic logic unit for processing incoming data and first pass pre-processed data, multiplier and accumulator unit for performing mathematical operations on DCT/IDCT data, and output buffer and arithmetic logic unit for processing first pass pre-processed data and outgoing data. Also provided is an interleaved random access memory for storing DCT/IDCT data during various stages of processing.