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公开(公告)号：EP3809098A1
公开(公告)日：2021-04-21
申请号：EP19203645.7
申请日：2019-10-16
申请人： AMS AG
发明人： Colombo, Matteo
摘要： A sensor front-end (1) is presented for processing a measurement signal (MS) from a sensing unit (2), wherein the sensing unit (2) is configured to receive a stimulus signal (ST) from an evaluation unit (10) of the sensor front-end (1), generate the measurement signal (MS) from the stimulus signal (ST) by altering an amplitude of the stimulus signal (ST) based on a measurement parameter, and provide the measurement signal (MS) to the evaluation unit (10). The sensor front-end (1) comprises the evaluation unit (10) that is configured to generate a simulated measurement signal (MSS) from the stimulus signal (ST) by controlling an amplitude of the stimulus signal (ST) based on a predetermined control variable (CV), to generate a simulated output signal (OSS) based on the stimulus signal (ST) and the simulated measurement signal (MSS), and to determine an error condition based on a comparison of the simulated output signal (OSS) and the predetermined control variable (CV) or a signal derived from the predetermined control variable (CV).
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公开(公告)号：EP2521263B1
公开(公告)日：2018-09-05
申请号：EP11164491.0
申请日：2011-05-02
申请人： ams AG
发明人： Colombo, Matteo , Fiocchi, Carlo
CPC分类号： H03K5/1515 , H02M1/08 , H02M1/38 , H02M3/1588 , H03K7/08 , Y02B70/1466
摘要： The present invention relates to a control circuit arrangement for pulse-width modulated DC/DC converters. The arrangement comprises a phase generator (10) for a complementary driver (20) adapted to provide respective gate signals to a first and second driver transistor in response to a control signal (p_off_pwm). A clock control circuit (30) receives a clock signal (x_clk) and a pulse-width modulated signal and provides the control signal (p_off_pwm) in response to a signal edge of the pulse-width modulated signal and the clock signal (x_clk) applied thereto. A mode selection input terminal receives a mode selection signal to select a first mode or a second mode of operation. The phase generator is adapted in the first mode to provide each of the gate signals in response to the control signal and in response to the respective other gate signal. In the second mode of operation, it provides each gate signal in response to the control signal.
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公开(公告)号：EP3401932A1
公开(公告)日：2018-11-14
申请号：EP17170814.2
申请日：2017-05-12
申请人： AMS AG
发明人： Colombo, Matteo , Paglino, Lorenzo
CPC分类号： H01C10/06 , H01C10/14 , H01C17/22 , H01L23/525
摘要： An electric circuit (3) for trimming a resistance of a resistor (Rfix) comprises a current path (100) including a first section (110) and at least one second section (150), wherein the first and the at least one second section (110, 150) are connected in series in the current path (100). The first section (110) of the current path includes the resistor (Rfix) to be trimmed. The at least one second section (150) of the current path (100) includes a first current branch (151) and a second current branch (152). The first current branch (151) of the at least one second section (150) of the current path (100) includes a first trimming resistor (R150a) and a second trimming resistor (R150b) being connected in parallel. The second current branch (152) of the at least one second section (150) of the current path (100) includes a third trimming resistor (R150c) and a fourth trimming resistor (R150d) being connected in parallel.
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